ECC Functions

Functions that related to the ECC feature. More...

Macros
#define	ECC_ERROR_RAMID_MASK_ICACHE   1U
#define	ECC_ERROR_RAMID_MASK_DCACHE   2U
#define	ECC_ERROR_RAMID_MASK_TLB   4U
#define	ECC_ERROR_RAMID_MASK_ILM   8U
#define	ECC_ERROR_RAMID_MASK_DLM   16U

Functions
__STATIC_FORCEINLINE int32_t	ECC_IsGlobalSupportECC (void)
	Check if the core globally supports ECC. More...
__STATIC_FORCEINLINE int32_t	ECC_IsICacheSupportECC (void)
	Check if I-Cache supports ECC. More...
__STATIC_FORCEINLINE int32_t	ECC_IsDCacheSupportECC (void)
	Check if D-Cache supports ECC. More...
__STATIC_FORCEINLINE int32_t	ECC_IsTLBSupportECC (void)
	Check if TLB supports ECC. More...
__STATIC_FORCEINLINE int32_t	ECC_IsILMSupportECC (void)
	Check if ILM supports ECC. More...
__STATIC_FORCEINLINE int32_t	ECC_IsDLMSupportECC (void)
	Check if DLM supports ECC. More...
__STATIC_FORCEINLINE int32_t	ECC_IsXorErrorInjectMode (void)
	Check if XOR error injection mode is supported. More...
__STATIC_FORCEINLINE void	ECC_EnableICacheECC (void)
	Enable ECC for I-Cache. More...
__STATIC_FORCEINLINE void	ECC_DisableICacheECC (void)
	Disable ECC for I-Cache. More...
__STATIC_FORCEINLINE void	ECC_EnableICacheECCExcp (void)
	Enable ECC exception for I-Cache. More...
__STATIC_FORCEINLINE void	ECC_DisableICacheECCExcp (void)
	Disable ECC exception for I-Cache. More...
__STATIC_FORCEINLINE void	ECC_EnableICacheECCCheck (void)
	Enable ECC checking for I-Cache. More...
__STATIC_FORCEINLINE void	ECC_DisableICacheECCCheck (void)
	Disable ECC checking for I-Cache. More...
__STATIC_FORCEINLINE void	ECC_EnableDCacheECC (void)
	Enable ECC for D-Cache. More...
__STATIC_FORCEINLINE void	ECC_DisableDCacheECC (void)
	Disable ECC for D-Cache. More...
__STATIC_FORCEINLINE void	ECC_EnableDCacheECCExcp (void)
	Enable ECC exception for D-Cache. More...
__STATIC_FORCEINLINE void	ECC_DisableDCacheECCExcp (void)
	Disable ECC exception for D-Cache. More...
__STATIC_FORCEINLINE void	ECC_EnableDCacheECCCheck (void)
	Enable ECC checking for D-Cache. More...
__STATIC_FORCEINLINE void	ECC_DisableDCacheECCCheck (void)
	Disable ECC checking for D-Cache. More...
__STATIC_FORCEINLINE void	ECC_ICacheTRamErrInject (uint32_t ecc_code, void *addr)
	Inject error into I-Cache Tag RAM. More...
__STATIC_FORCEINLINE void	ECC_ICacheDRamErrInject (uint32_t ecc_code, void *addr)
	Inject error into I-Cache Data RAM. More...
__STATIC_FORCEINLINE void	ECC_ICacheErrRestore (void *addr)
	Restore I-Cache error at specified address. More...
__STATIC_FORCEINLINE void	ECC_DCacheTRamErrInject (uint32_t ecc_code, void *addr)
	Inject error into D-Cache Tag RAM. More...
__STATIC_FORCEINLINE void	ECC_DCacheDRamErrInject (uint32_t ecc_code, void *addr)
	Inject error into D-Cache Data RAM. More...
__STATIC_FORCEINLINE void	ECC_DCacheErrRestore (void *addr)
	Restore D-Cache error at specified address. More...
__STATIC_FORCEINLINE void	ECC_EnableILM (void)
	Enable ILM. More...
__STATIC_FORCEINLINE void	ECC_DisableILM (void)
	Disable ILM. More...
__STATIC_FORCEINLINE void	ECC_EnableILMECC (void)
	Enable ECC for ILM. More...
__STATIC_FORCEINLINE void	ECC_DisableILMECC (void)
	Disable ECC for ILM. More...
__STATIC_FORCEINLINE void	ECC_EnableILMECCExcp (void)
	Enable ECC exception for ILM. More...
__STATIC_FORCEINLINE void	ECC_DisableILMECCExcp (void)
	Disable ECC exception for ILM. More...
__STATIC_FORCEINLINE void	ECC_EnableILMECCCheck (void)
	Enable ECC checking for ILM. More...
__STATIC_FORCEINLINE void	ECC_DisableILMECCCheck (void)
	Disable ECC checking for ILM. More...
__STATIC_FORCEINLINE void	ECC_ILMErrInject (uint32_t ecc_code, void *addr)
	Inject error into ILM. More...
__STATIC_FORCEINLINE void	ECC_ILMErrRestore (void *addr)
	Restore ILM error at specified address. More...
__STATIC_FORCEINLINE void	ECC_EnableDLM (void)
	Enable DLM. More...
__STATIC_FORCEINLINE void	ECC_DisableDLM (void)
	Disable DLM. More...
__STATIC_FORCEINLINE void	ECC_EnableDLMECC (void)
	Enable ECC for DLM. More...
__STATIC_FORCEINLINE void	ECC_DisableDLMECC (void)
	Disable ECC for DLM. More...
__STATIC_FORCEINLINE void	ECC_EnableDLMECCExcp (void)
	Enable ECC exception for DLM. More...
__STATIC_FORCEINLINE void	ECC_DisableDLMECCExcp (void)
	Disable ECC exception for DLM. More...
__STATIC_FORCEINLINE void	ECC_EnableDLMECCCheck (void)
	Enable ECC checking for DLM. More...
__STATIC_FORCEINLINE void	ECC_DisableDLMECCCheck (void)
	Disable ECC checking for DLM. More...
__STATIC_FORCEINLINE void	ECC_DLMErrInject (uint32_t ecc_code, void *addr)
	Inject error into DLM. More...
__STATIC_FORCEINLINE void	ECC_DLMErrRestore (void *addr)
	Restore DLM error at specified address. More...
__STATIC_FORCEINLINE int32_t	ECC_IsAnySingleBitErrorOccured (void)
	Check if any single-bit error has occurred. More...
__STATIC_FORCEINLINE int32_t	ECC_IsICacheSingleBitErrorOccured (void)
	Check if I-Cache single-bit error has occurred. More...
__STATIC_FORCEINLINE int32_t	ECC_IsDCacheSingleBitErrorOccured (void)
	Check if D-Cache single-bit error has occurred. More...
__STATIC_FORCEINLINE int32_t	ECC_IsTLBSingleBitErrorOccured (void)
	Check if TLB single-bit error has occurred. More...
__STATIC_FORCEINLINE int32_t	ECC_IsILMSingleBitErrorOccured (void)
	Check if ILM single-bit error has occurred. More...
__STATIC_FORCEINLINE int32_t	ECC_IsDLMSingleBitErrorOccured (void)
	Check if DLM single-bit error has occurred. More...
__STATIC_FORCEINLINE void	ECC_ClearAllSingleBitError (void)
	Clear all single-bit errors. More...
__STATIC_FORCEINLINE void	ECC_ClearICacheSingleBitError (void)
	Clear I-Cache single-bit error. More...
__STATIC_FORCEINLINE void	ECC_ClearDCacheSingleBitError (void)
	Clear D-Cache single-bit error. More...
__STATIC_FORCEINLINE void	ECC_ClearTLBSingleBitError (void)
	Clear TLB single-bit error. More...
__STATIC_FORCEINLINE void	ECC_ClearILMSingleBitError (void)
	Clear ILM single-bit error. More...
__STATIC_FORCEINLINE void	ECC_ClearDLMSingleBitError (void)
	Clear DLM single-bit error. More...
__STATIC_FORCEINLINE int32_t	ECC_IsAnyDoubleBitErrorOccured (void)
	Check if any double-bit error has occurred. More...
__STATIC_FORCEINLINE int32_t	ECC_IsICacheDoubleBitErrorOccured (void)
	Check if I-Cache double-bit error has occurred. More...
__STATIC_FORCEINLINE int32_t	ECC_IsDCacheDoubleBitErrorOccured (void)
	Check if D-Cache double-bit error has occurred. More...
__STATIC_FORCEINLINE int32_t	ECC_IsTLBDoubleBitErrorOccured (void)
	Check if TLB double-bit error has occurred. More...
__STATIC_FORCEINLINE int32_t	ECC_IsILMDoubleBitErrorOccured (void)
	Check if ILM double-bit error has occurred. More...
__STATIC_FORCEINLINE int32_t	ECC_IsDLMDoubleBitErrorOccured (void)
	Check if DLM double-bit error has occurred. More...
__STATIC_FORCEINLINE void	ECC_ClearAllDoubleBitError (void)
	Clear all double-bit errors. More...
__STATIC_FORCEINLINE void	ECC_ClearICacheDoubleBitError (void)
	Clear I-Cache double-bit error. More...
__STATIC_FORCEINLINE void	ECC_ClearDCacheDoubleBitError (void)
	Clear D-Cache double-bit error. More...
__STATIC_FORCEINLINE void	ECC_ClearTLBDoubleBitError (void)
	Clear TLB double-bit error. More...
__STATIC_FORCEINLINE void	ECC_ClearILMDoubleBitError (void)
	Clear ILM double-bit error. More...
__STATIC_FORCEINLINE void	ECC_ClearDLMDoubleBitError (void)
	Clear DLM double-bit error. More...
static uint8_t	ECC_GenerateECCCodeU32 (uint32_t a)
	Generate ECC code for a 32-bit value. More...
static uint8_t	ECC_GenerateECCCodeU64 (uint64_t a)
	Generate ECC code for a 64-bit value. More...

Detailed Description

Functions that related to the ECC feature.

These functions provide access to the Error Correction Code (ECC) feature available in Nuclei N/NX processor cores. ECC is a memory protection mechanism that can detect and correct single-bit errors and detect double-bit errors in memory systems such as caches and local memories.

The ECC feature includes:

• Detection of ECC support in various memory components (I-Cache, D-Cache, ILM, DLM, TLB)
• Control functions to enable/disable ECC for different memory components
• Error injection capabilities for testing purposes
• Error detection and clearing functions for both single-bit and double-bit errors
• Configuration of ECC exception handling

Macro Definition Documentation

ECC_ERROR_RAMID_MASK_DCACHE

#define ECC_ERROR_RAMID_MASK_DCACHE   2U

Definition at line 654 of file core_feature_ecc.h.

ECC_ERROR_RAMID_MASK_DLM

#define ECC_ERROR_RAMID_MASK_DLM   16U

Definition at line 657 of file core_feature_ecc.h.

ECC_ERROR_RAMID_MASK_ICACHE

#define ECC_ERROR_RAMID_MASK_ICACHE   1U

Definition at line 653 of file core_feature_ecc.h.

ECC_ERROR_RAMID_MASK_ILM

#define ECC_ERROR_RAMID_MASK_ILM   8U

Definition at line 656 of file core_feature_ecc.h.

ECC_ERROR_RAMID_MASK_TLB

#define ECC_ERROR_RAMID_MASK_TLB   4U

Definition at line 655 of file core_feature_ecc.h.

Function Documentation

ECC_ClearAllDoubleBitError()

__STATIC_FORCEINLINE void ECC_ClearAllDoubleBitError

(

void

)

Clear all double-bit errors.

This function clears all double-bit errors by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 887 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_RAMID);
}

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_RAMID.

ECC_ClearAllSingleBitError()

__STATIC_FORCEINLINE void ECC_ClearAllSingleBitError

(

void

)

Clear all single-bit errors.

This function clears all single-bit errors by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 743 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_SRAMID);
}

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_SRAMID.

ECC_ClearDCacheDoubleBitError()

__STATIC_FORCEINLINE void ECC_ClearDCacheDoubleBitError

(

void

)

Clear D-Cache double-bit error.

This function clears the double-bit error in the D-Cache by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 909 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_RAMID_DC);
}

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_RAMID_DC.

ECC_ClearDCacheSingleBitError()

__STATIC_FORCEINLINE void ECC_ClearDCacheSingleBitError

(

void

)

Clear D-Cache single-bit error.

This function clears the single-bit error in the D-Cache by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 765 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_SRAMID_DC);
}

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_SRAMID_DC.

ECC_ClearDLMDoubleBitError()

__STATIC_FORCEINLINE void ECC_ClearDLMDoubleBitError

(

void

)

Clear DLM double-bit error.

This function clears the double-bit error in the DLM by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 942 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_RAMID_DLM);
}

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_RAMID_DLM.

ECC_ClearDLMSingleBitError()

__STATIC_FORCEINLINE void ECC_ClearDLMSingleBitError

(

void

)

Clear DLM single-bit error.

This function clears the single-bit error in the DLM by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 798 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_SRAMID_DLM);
}

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_SRAMID_DLM.

ECC_ClearICacheDoubleBitError()

__STATIC_FORCEINLINE void ECC_ClearICacheDoubleBitError

(

void

)

Clear I-Cache double-bit error.

This function clears the double-bit error in the I-Cache by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 898 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_RAMID_IC);
}

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_RAMID_IC.

ECC_ClearICacheSingleBitError()

__STATIC_FORCEINLINE void ECC_ClearICacheSingleBitError

(

void

)

Clear I-Cache single-bit error.

This function clears the single-bit error in the I-Cache by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 754 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_SRAMID_IC);
}

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_SRAMID_IC.

ECC_ClearILMDoubleBitError()

__STATIC_FORCEINLINE void ECC_ClearILMDoubleBitError

(

void

)

Clear ILM double-bit error.

This function clears the double-bit error in the ILM by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 931 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_RAMID_ILM);
}

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_RAMID_ILM.

ECC_ClearILMSingleBitError()

__STATIC_FORCEINLINE void ECC_ClearILMSingleBitError

(

void

)

Clear ILM single-bit error.

This function clears the single-bit error in the ILM by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 787 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_SRAMID_ILM);
}

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_SRAMID_ILM.

ECC_ClearTLBDoubleBitError()

__STATIC_FORCEINLINE void ECC_ClearTLBDoubleBitError

(

void

)

Clear TLB double-bit error.

This function clears the double-bit error in the TLB by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 920 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_RAMID_TLB);
}

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_RAMID_TLB.

ECC_ClearTLBSingleBitError()

__STATIC_FORCEINLINE void ECC_ClearTLBSingleBitError

(

void

)

Clear TLB single-bit error.

This function clears the single-bit error in the TLB by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 776 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_SRAMID_TLB);
}

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_SRAMID_TLB.

ECC_DCacheDRamErrInject()

__STATIC_FORCEINLINE void ECC_DCacheDRamErrInject	(	uint32_t	ecc_code,
		void *	addr
	)

Inject error into D-Cache Data RAM.

This function injects an error into the D-Cache Data RAM at the specified address with the given ECC code.

Parameters

[in]	ecc_code	ECC code to inject
[in]	addr	Address where error should be injected

Definition at line 389 of file core_feature_ecc.h.

{
    /* Write ecc_code into mecc_code csr also clear all error status */
    __RV_CSR_WRITE(CSR_MECC_CODE, ecc_code);
    ECC_DisableDCacheECCCheck();
    MFlushInvalDCacheLine((unsigned long)addr);
    __RWMB();
    __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_DC_DRAM_ECC_INJ_EN);
    MLockDCacheLine((unsigned long)addr);
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_DC_DRAM_ECC_INJ_EN);
    __RWMB();
    ECC_EnableDCacheECCCheck();
}

References __RV_CSR_CLEAR, __RV_CSR_SET, __RV_CSR_WRITE, __RWMB, CSR_MCACHE_CTL, CSR_MECC_CODE, ECC_DisableDCacheECCCheck(), ECC_EnableDCacheECCCheck(), MCACHE_CTL_DC_DRAM_ECC_INJ_EN, MFlushInvalDCacheLine(), and MLockDCacheLine().

ECC_DCacheErrRestore()

__STATIC_FORCEINLINE void ECC_DCacheErrRestore

(

void *

addr

)

Restore D-Cache error at specified address.

This function restores the correct ECC code for the D-Cache line at the specified address.

Parameters

[in]

addr

Address to restore

Definition at line 409 of file core_feature_ecc.h.

{
    ECC_DisableDCacheECCCheck();
    MFlushInvalDCacheLine((unsigned long)addr);
    MLockDCacheLine((unsigned long)addr);
    ECC_EnableDCacheECCCheck();
}

References ECC_DisableDCacheECCCheck(), ECC_EnableDCacheECCCheck(), MFlushInvalDCacheLine(), and MLockDCacheLine().

ECC_DCacheTRamErrInject()

__STATIC_FORCEINLINE void ECC_DCacheTRamErrInject	(	uint32_t	ecc_code,
		void *	addr
	)

Inject error into D-Cache Tag RAM.

This function injects an error into the D-Cache Tag RAM at the specified address with the given ECC code.

Parameters

[in]	ecc_code	ECC code to inject
[in]	addr	Address where error should be injected

Definition at line 367 of file core_feature_ecc.h.

{
    /* Write ecc_code into mecc_code csr also clear all error status */
    __RV_CSR_WRITE(CSR_MECC_CODE, ecc_code);
    ECC_DisableDCacheECCCheck();
    MFlushInvalDCacheLine((unsigned long)addr);
    __RWMB();
    __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_DC_TRAM_ECC_INJ_EN);
    MLockDCacheLine((unsigned long)addr);
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_DC_TRAM_ECC_INJ_EN);
    __RWMB();
    ECC_EnableDCacheECCCheck();
}

References __RV_CSR_CLEAR, __RV_CSR_SET, __RV_CSR_WRITE, __RWMB, CSR_MCACHE_CTL, CSR_MECC_CODE, ECC_DisableDCacheECCCheck(), ECC_EnableDCacheECCCheck(), MCACHE_CTL_DC_TRAM_ECC_INJ_EN, MFlushInvalDCacheLine(), and MLockDCacheLine().

ECC_DisableDCacheECC()

__STATIC_FORCEINLINE void ECC_DisableDCacheECC

(

void

)

Disable ECC for D-Cache.

This function disables ECC for the data cache by clearing the appropriate bit in the machine cache control CSR.

Definition at line 253 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_EN);
}

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_DC_ECC_EN.

ECC_DisableDCacheECCCheck()

__STATIC_FORCEINLINE void ECC_DisableDCacheECCCheck

(

void

)

Disable ECC checking for D-Cache.

This function disables ECC checking for the data cache by clearing the appropriate bit in the machine cache control CSR.

Definition at line 297 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_CHK_EN);
}

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_DC_ECC_CHK_EN.

Referenced by ECC_DCacheDRamErrInject(), ECC_DCacheErrRestore(), and ECC_DCacheTRamErrInject().

ECC_DisableDCacheECCExcp()

__STATIC_FORCEINLINE void ECC_DisableDCacheECCExcp

(

void

)

Disable ECC exception for D-Cache.

This function disables ECC exception for the data cache by clearing the appropriate bit in the machine cache control CSR.

Definition at line 275 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_EXCP_EN);
}

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_DC_ECC_EXCP_EN.

ECC_DisableDLM()

__STATIC_FORCEINLINE void ECC_DisableDLM

(

void

)

Disable DLM.

This function disables DLM by clearing the appropriate bit in the machine DLM control CSR.

Definition at line 551 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MDLM_CTL, MDLM_CTL_DLM_EN);
}

References __RV_CSR_CLEAR, CSR_MDLM_CTL, and MDLM_CTL_DLM_EN.

ECC_DisableDLMECC()

__STATIC_FORCEINLINE void ECC_DisableDLMECC

(

void

)

Disable ECC for DLM.

This function disables ECC for DLM by clearing the appropriate bit in the machine DLM control CSR.

Definition at line 571 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_EN);
}

References __RV_CSR_CLEAR, CSR_MDLM_CTL, and MDLM_CTL_DLM_ECC_EN.

ECC_DisableDLMECCCheck()

__STATIC_FORCEINLINE void ECC_DisableDLMECCCheck

(

void

)

Disable ECC checking for DLM.

This function disables ECC checking for DLM by clearing the appropriate bit in the machine DLM control CSR.

Definition at line 611 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_CHK_EN);
}

References __RV_CSR_CLEAR, CSR_MDLM_CTL, and MDLM_CTL_DLM_ECC_CHK_EN.

Referenced by ECC_DLMErrInject(), and ECC_DLMErrRestore().

ECC_DisableDLMECCExcp()

__STATIC_FORCEINLINE void ECC_DisableDLMECCExcp

(

void

)

Disable ECC exception for DLM.

This function disables ECC exception for DLM by clearing the appropriate bit in the machine DLM control CSR.

Definition at line 591 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_EXCP_EN);
}

References __RV_CSR_CLEAR, CSR_MDLM_CTL, and MDLM_CTL_DLM_ECC_EXCP_EN.

ECC_DisableICacheECC()

__STATIC_FORCEINLINE void ECC_DisableICacheECC

(

void

)

Disable ECC for I-Cache.

This function disables ECC for the instruction cache by clearing the appropriate bit in the machine cache control CSR.

Definition at line 187 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_EN);
}

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_IC_ECC_EN.

ECC_DisableICacheECCCheck()

__STATIC_FORCEINLINE void ECC_DisableICacheECCCheck

(

void

)

Disable ECC checking for I-Cache.

This function disables ECC checking for the instruction cache by clearing the appropriate bit in the machine cache control CSR.

Definition at line 231 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_CHK_EN);
}

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_IC_ECC_CHK_EN.

ECC_DisableICacheECCExcp()

__STATIC_FORCEINLINE void ECC_DisableICacheECCExcp

(

void

)

Disable ECC exception for I-Cache.

This function disables ECC exception for the instruction cache by clearing the appropriate bit in the machine cache control CSR.

Definition at line 209 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_EXCP_EN);
}

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_IC_ECC_EXCP_EN.

ECC_DisableILM()

__STATIC_FORCEINLINE void ECC_DisableILM

(

void

)

Disable ILM.

This function disables ILM by clearing the appropriate bit in the machine ILM control CSR.

Definition at line 434 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MILM_CTL, MILM_CTL_ILM_EN);
}

References __RV_CSR_CLEAR, CSR_MILM_CTL, and MILM_CTL_ILM_EN.

ECC_DisableILMECC()

__STATIC_FORCEINLINE void ECC_DisableILMECC

(

void

)

Disable ECC for ILM.

This function disables ECC for ILM by clearing the appropriate bit in the machine ILM control CSR.

Definition at line 454 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MILM_CTL, MILM_CTL_ILM_ECC_EN);
}

References __RV_CSR_CLEAR, CSR_MILM_CTL, and MILM_CTL_ILM_ECC_EN.

ECC_DisableILMECCCheck()

__STATIC_FORCEINLINE void ECC_DisableILMECCCheck

(

void

)

Disable ECC checking for ILM.

This function disables ECC checking for ILM by clearing the appropriate bit in the machine ILM control CSR.

Definition at line 494 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MILM_CTL, MILM_CTL_ILM_ECC_CHK_EN);
}

References __RV_CSR_CLEAR, CSR_MILM_CTL, and MILM_CTL_ILM_ECC_CHK_EN.

Referenced by ECC_ILMErrInject(), and ECC_ILMErrRestore().

ECC_DisableILMECCExcp()

__STATIC_FORCEINLINE void ECC_DisableILMECCExcp

(

void

)

Disable ECC exception for ILM.

This function disables ECC exception for ILM by clearing the appropriate bit in the machine ILM control CSR.

Definition at line 474 of file core_feature_ecc.h.

{
    __RV_CSR_CLEAR(CSR_MILM_CTL, MILM_CTL_ILM_ECC_EXCP_EN);
}

References __RV_CSR_CLEAR, CSR_MILM_CTL, and MILM_CTL_ILM_ECC_EXCP_EN.

ECC_DLMErrInject()

__STATIC_FORCEINLINE void ECC_DLMErrInject	(	uint32_t	ecc_code,
		void *	addr
	)

Inject error into DLM.

This function injects an error into the DLM at the specified address with the given ECC code.

Parameters

[in]	ecc_code	ECC code to inject
[in]	addr	Address where error should be injected

Definition at line 623 of file core_feature_ecc.h.

{
    /* Write ecc_code into mecc_code csr also clear all error status */
    __RV_CSR_WRITE(CSR_MECC_CODE, ecc_code);
    ECC_DisableDLMECCCheck();
    uint32_t val = __LW(addr);
    __RWMB(); // make sure setting the ECC_INJ_EN bit before any other memory access
    __RV_CSR_SET(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_INJ_EN);
    __SW(addr, val);
    __RWMB(); // make sure the error injection is finished
    __RV_CSR_CLEAR(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_INJ_EN);
    __RWMB(); // make sure clearing the ECC_INJ_EN bit before any other memory access
    ECC_EnableDLMECCCheck();
}

References __LW(), __RV_CSR_CLEAR, __RV_CSR_SET, __RV_CSR_WRITE, __RWMB, __SW(), CSR_MDLM_CTL, CSR_MECC_CODE, ECC_DisableDLMECCCheck(), ECC_EnableDLMECCCheck(), and MDLM_CTL_DLM_ECC_INJ_EN.

ECC_DLMErrRestore()

__STATIC_FORCEINLINE void ECC_DLMErrRestore

(

void *

addr

)

Restore DLM error at specified address.

This function restores the correct ECC code for the DLM at the specified address.

Parameters

[in]

addr

Address to restore

Definition at line 644 of file core_feature_ecc.h.

{
    ECC_DisableDLMECCCheck();
    __RWMB();
    __SW(addr, __LW(addr));
    __RWMB();
    ECC_EnableDLMECCCheck();
}

References __LW(), __RWMB, __SW(), ECC_DisableDLMECCCheck(), and ECC_EnableDLMECCCheck().

ECC_EnableDCacheECC()

__STATIC_FORCEINLINE void ECC_EnableDCacheECC

(

void

)

Enable ECC for D-Cache.

This function enables ECC for the data cache by setting the appropriate bit in the machine cache control CSR.

Definition at line 242 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_EN);
}

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_DC_ECC_EN.

ECC_EnableDCacheECCCheck()

__STATIC_FORCEINLINE void ECC_EnableDCacheECCCheck

(

void

)

Enable ECC checking for D-Cache.

This function enables ECC checking for the data cache by setting the appropriate bit in the machine cache control CSR.

Definition at line 286 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_CHK_EN);
}

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_DC_ECC_CHK_EN.

Referenced by ECC_DCacheDRamErrInject(), ECC_DCacheErrRestore(), and ECC_DCacheTRamErrInject().

ECC_EnableDCacheECCExcp()

__STATIC_FORCEINLINE void ECC_EnableDCacheECCExcp

(

void

)

Enable ECC exception for D-Cache.

This function enables ECC exception for the data cache by setting the appropriate bit in the machine cache control CSR.

Definition at line 264 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_EXCP_EN);
}

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_DC_ECC_EXCP_EN.

ECC_EnableDLM()

__STATIC_FORCEINLINE void ECC_EnableDLM

(

void

)

Enable DLM.

This function enables DLM by setting the appropriate bit in the machine DLM control CSR.

Definition at line 541 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MDLM_CTL, MDLM_CTL_DLM_EN);
}

References __RV_CSR_SET, CSR_MDLM_CTL, and MDLM_CTL_DLM_EN.

ECC_EnableDLMECC()

__STATIC_FORCEINLINE void ECC_EnableDLMECC

(

void

)

Enable ECC for DLM.

This function enables ECC for DLM by setting the appropriate bit in the machine DLM control CSR.

Definition at line 561 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_EN);
}

References __RV_CSR_SET, CSR_MDLM_CTL, and MDLM_CTL_DLM_ECC_EN.

ECC_EnableDLMECCCheck()

__STATIC_FORCEINLINE void ECC_EnableDLMECCCheck

(

void

)

Enable ECC checking for DLM.

This function enables ECC checking for DLM by setting the appropriate bit in the machine DLM control CSR.

Definition at line 601 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_CHK_EN);
}

References __RV_CSR_SET, CSR_MDLM_CTL, and MDLM_CTL_DLM_ECC_CHK_EN.

Referenced by ECC_DLMErrInject(), and ECC_DLMErrRestore().

ECC_EnableDLMECCExcp()

__STATIC_FORCEINLINE void ECC_EnableDLMECCExcp

(

void

)

Enable ECC exception for DLM.

This function enables ECC exception for DLM by setting the appropriate bit in the machine DLM control CSR.

Definition at line 581 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_EXCP_EN);
}

References __RV_CSR_SET, CSR_MDLM_CTL, and MDLM_CTL_DLM_ECC_EXCP_EN.

ECC_EnableICacheECC()

__STATIC_FORCEINLINE void ECC_EnableICacheECC

(

void

)

Enable ECC for I-Cache.

This function enables ECC for the instruction cache by setting the appropriate bit in the machine cache control CSR.

Definition at line 176 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_EN);
}

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_IC_ECC_EN.

ECC_EnableICacheECCCheck()

__STATIC_FORCEINLINE void ECC_EnableICacheECCCheck

(

void

)

Enable ECC checking for I-Cache.

This function enables ECC checking for the instruction cache by setting the appropriate bit in the machine cache control CSR.

Definition at line 220 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_CHK_EN);
}

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_IC_ECC_CHK_EN.

ECC_EnableICacheECCExcp()

__STATIC_FORCEINLINE void ECC_EnableICacheECCExcp

(

void

)

Enable ECC exception for I-Cache.

This function enables ECC exception for the instruction cache by setting the appropriate bit in the machine cache control CSR.

Definition at line 198 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_EXCP_EN);
}

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_IC_ECC_EXCP_EN.

ECC_EnableILM()

__STATIC_FORCEINLINE void ECC_EnableILM

(

void

)

Enable ILM.

This function enables ILM by setting the appropriate bit in the machine ILM control CSR.

Definition at line 424 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MILM_CTL, MILM_CTL_ILM_EN);
}

References __RV_CSR_SET, CSR_MILM_CTL, and MILM_CTL_ILM_EN.

ECC_EnableILMECC()

__STATIC_FORCEINLINE void ECC_EnableILMECC

(

void

)

Enable ECC for ILM.

This function enables ECC for ILM by setting the appropriate bit in the machine ILM control CSR.

Definition at line 444 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MILM_CTL, MILM_CTL_ILM_ECC_EN);
}

References __RV_CSR_SET, CSR_MILM_CTL, and MILM_CTL_ILM_ECC_EN.

ECC_EnableILMECCCheck()

__STATIC_FORCEINLINE void ECC_EnableILMECCCheck

(

void

)

Enable ECC checking for ILM.

This function enables ECC checking for ILM by setting the appropriate bit in the machine ILM control CSR.

Definition at line 484 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MILM_CTL, MILM_CTL_ILM_ECC_CHK_EN);
}

References __RV_CSR_SET, CSR_MILM_CTL, and MILM_CTL_ILM_ECC_CHK_EN.

Referenced by ECC_ILMErrInject(), and ECC_ILMErrRestore().

ECC_EnableILMECCExcp()

__STATIC_FORCEINLINE void ECC_EnableILMECCExcp

(

void

)

Enable ECC exception for ILM.

This function enables ECC exception for ILM by setting the appropriate bit in the machine ILM control CSR.

Definition at line 464 of file core_feature_ecc.h.

{
    __RV_CSR_SET(CSR_MILM_CTL, MILM_CTL_ILM_ECC_EXCP_EN);
}

References __RV_CSR_SET, CSR_MILM_CTL, and MILM_CTL_ILM_ECC_EXCP_EN.

ECC_GenerateECCCodeU32()

static uint8_t ECC_GenerateECCCodeU32 ( uint32_t  a )

static

Generate ECC code for a 32-bit value.

This function calculates the ECC code for a 32-bit input value using Hamming code algorithm. It generates a 7-bit ECC code that can be used to detect and correct single-bit errors and detect double-bit errors.

Parameters

[in]

a

32-bit value for which ECC code is to be generated

Returns

8-bit ECC code (7 bits used, 1 bit unused)

Definition at line 956 of file core_feature_ecc.h.

{
    uint8_t ecc_bits = 0;
    uint8_t ecc_bit_0 = ((a >> 0) & 1) ^ ((a >> 1) & 1) ^ ((a >> 3) & 1) ^ ((a >> 4) & 1) ^
                        ((a >> 6) & 1) ^ ((a >> 8) & 1) ^ ((a >> 10) & 1) ^ ((a >> 12) & 1) ^
                        ((a >> 14) & 1) ^ ((a >> 17) & 1) ^ ((a >> 19) & 1) ^ ((a >> 20) & 1) ^
                        ((a >> 24) & 1) ^ ((a >> 28) & 1);
    uint8_t ecc_bit_1 = ((a >> 0) & 1) ^ ((a >> 2) & 1) ^ ((a >> 3) & 1) ^ ((a >> 5) & 1) ^
                        ((a >> 6) & 1) ^ ((a >> 9) & 1) ^ ((a >> 11) & 1) ^ ((a >> 12) & 1) ^
                        ((a >> 15) & 1) ^ ((a >> 20) & 1) ^ ((a >> 22) & 1) ^ ((a >> 25) & 1) ^
                        ((a >> 29) & 1);
    uint8_t ecc_bit_2 = ((a >> 1) & 1) ^ ((a >> 2) & 1) ^ ((a >> 3) & 1) ^ ((a >> 7) & 1) ^
                        ((a >> 8) & 1) ^ ((a >> 9) & 1) ^ ((a >> 13) & 1) ^ ((a >> 14) & 1) ^
                        ((a >> 15) & 1) ^ ((a >> 18) & 1) ^ ((a >> 21) & 1) ^ ((a >> 22) & 1) ^
                        ((a >> 26) & 1) ^ ((a >> 30) & 1);
    uint8_t ecc_bit_3 = ((a >> 4) & 1) ^ ((a >> 5) & 1) ^ ((a >> 6) & 1) ^ ((a >> 7) & 1) ^
                        ((a >> 8) & 1) ^ ((a >> 9) & 1) ^ ((a >> 16) & 1) ^ ((a >> 17) & 1) ^
                        ((a >> 18) & 1) ^ ((a >> 23) & 1) ^ ((a >> 24) & 1) ^ ((a >> 25) & 1) ^
                        ((a >> 26) & 1) ^ ((a >> 31) & 1);
    uint8_t ecc_bit_4 = ((a >> 10) & 1) ^ ((a >> 11) & 1) ^ ((a >> 12) & 1) ^ ((a >> 13) & 1) ^
                        ((a >> 14) & 1) ^ ((a >> 15) & 1) ^ ((a >> 16) & 1) ^ ((a >> 17) & 1) ^
                        ((a >> 18) & 1) ^ ((a >> 27) & 1) ^ ((a >> 28) & 1) ^ ((a >> 29) & 1) ^
                        ((a >> 30) & 1) ^ ((a >> 31) & 1);
    uint8_t ecc_bit_5 = ((a >> 19) & 1) ^ ((a >> 20) & 1) ^ ((a >> 21) & 1) ^ ((a >> 22) & 1) ^
                        ((a >> 23) & 1) ^ ((a >> 24) & 1) ^ ((a >> 25) & 1) ^ ((a >> 26) & 1) ^
                        ((a >> 27) & 1) ^ ((a >> 28) & 1) ^ ((a >> 29) & 1) ^ ((a >> 30) & 1) ^
                        ((a >> 31) & 1);
    uint8_t ecc_bit_6 = ((a >> 0) & 1) ^ ((a >> 1) & 1) ^ ((a >> 2) & 1) ^ ((a >> 4) & 1) ^
                        ((a >> 5) & 1) ^ ((a >> 7) & 1) ^ ((a >> 10) & 1) ^ ((a >> 11) & 1) ^
                        ((a >> 13) & 1) ^ ((a >> 16) & 1) ^ ((a >> 19) & 1) ^ ((a >> 21) & 1) ^
                        ((a >> 23) & 1) ^ ((a >> 27) & 1);
    ecc_bits = (ecc_bit_6 << 6) | (ecc_bit_5 << 5) | (ecc_bit_4 << 4) | (ecc_bit_3 << 3) |
               (ecc_bit_2 << 2) | (ecc_bit_1 << 1) | ecc_bit_0;
    return ecc_bits;
}

ECC_GenerateECCCodeU64()

static uint8_t ECC_GenerateECCCodeU64 ( uint64_t  a )

static

Generate ECC code for a 64-bit value.

This function calculates the ECC for a 64-bit input value using Hamming code algorithm. It generates an 8-bit ECC code that can be used to detect and correct single-bit errors and detect double-bit errors.

Parameters

[in]

a

64-bit value for which ECC code is to be generated

Returns

8-bit ECC code

Definition at line 1001 of file core_feature_ecc.h.

{
    uint8_t ecc_bits = 0;
    uint8_t ecc_bit_0 =
        (((a >> 0) & 1) ^ ((a >> 1) & 1) ^ ((a >> 3) & 1) ^ ((a >> 4) & 1) ^ ((a >> 6) & 1) ^
         ((a >> 8) & 1) ^ ((a >> 10) & 1) ^ ((a >> 12) & 1) ^ ((a >> 14) & 1) ^ ((a >> 17) & 1) ^
         ((a >> 20) & 1) ^ ((a >> 22) & 1) ^ ((a >> 24) & 1) ^ ((a >> 27) & 1) ^ ((a >> 30) & 1) ^
         ((a >> 32) & 1) ^ ((a >> 36) & 1) ^ ((a >> 37) & 1) ^ ((a >> 38) & 1) ^ ((a >> 40) & 1) ^
         ((a >> 42) & 1) ^ ((a >> 45) & 1) ^ ((a >> 47) & 1) ^ ((a >> 51) & 1) ^ ((a >> 54) & 1) ^
         ((a >> 57) & 1));
    uint8_t ecc_bit_1 =
        (((a >> 0) & 1) ^ ((a >> 2) & 1) ^ ((a >> 3) & 1) ^ ((a >> 5) & 1) ^ ((a >> 6) & 1) ^
         ((a >> 9) & 1) ^ ((a >> 11) & 1) ^ ((a >> 12) & 1) ^ ((a >> 15) & 1) ^ ((a >> 18) & 1) ^
         ((a >> 21) & 1) ^ ((a >> 22) & 1) ^ ((a >> 25) & 1) ^ ((a >> 28) & 1) ^ ((a >> 30) & 1) ^
         ((a >> 33) & 1) ^ ((a >> 37) & 1) ^ ((a >> 39) & 1) ^ ((a >> 40) & 1) ^ ((a >> 43) & 1) ^
         ((a >> 46) & 1) ^ ((a >> 47) & 1) ^ ((a >> 49) & 1) ^ ((a >> 52) & 1) ^ ((a >> 58) & 1) ^
         ((a >> 63) & 1));
    uint8_t ecc_bit_2 =
        (((a >> 1) & 1) ^ ((a >> 2) & 1) ^ ((a >> 3) & 1) ^ ((a >> 7) & 1) ^ ((a >> 8) & 1) ^
         ((a >> 9) & 1) ^ ((a >> 13) & 1) ^ ((a >> 14) & 1) ^ ((a >> 15) & 1) ^ ((a >> 19) & 1) ^
         ((a >> 23) & 1) ^ ((a >> 24) & 1) ^ ((a >> 25) & 1) ^ ((a >> 29) & 1) ^ ((a >> 30) & 1) ^
         ((a >> 34) & 1) ^ ((a >> 41) & 1) ^ ((a >> 42) & 1) ^ ((a >> 43) & 1) ^ ((a >> 48) & 1) ^
         ((a >> 49) & 1) ^ ((a >> 53) & 1) ^ ((a >> 54) & 1) ^ ((a >> 59) & 1) ^ ((a >> 62) & 1) ^
         ((a >> 63) & 1));
    uint8_t ecc_bit_3 =
        (((a >> 4) & 1) ^ ((a >> 5) & 1) ^ ((a >> 6) & 1) ^ ((a >> 7) & 1) ^ ((a >> 8) & 1) ^
         ((a >> 9) & 1) ^ ((a >> 16) & 1) ^ ((a >> 17) & 1) ^ ((a >> 18) & 1) ^ ((a >> 19) & 1) ^
         ((a >> 26) & 1) ^ ((a >> 27) & 1) ^ ((a >> 28) & 1) ^ ((a >> 29) & 1) ^ ((a >> 30) & 1) ^
         ((a >> 35) & 1) ^ ((a >> 36) & 1) ^ ((a >> 37) & 1) ^ ((a >> 44) & 1) ^ ((a >> 45) & 1) ^
         ((a >> 46) & 1) ^ ((a >> 47) & 1) ^ ((a >> 48) & 1) ^ ((a >> 49) & 1) ^ ((a >> 55) & 1) ^
         ((a >> 60) & 1));
    uint8_t ecc_bit_4 =
        (((a >> 10) & 1) ^ ((a >> 11) & 1) ^ ((a >> 12) & 1) ^ ((a >> 13) & 1) ^ ((a >> 14) & 1) ^
         ((a >> 15) & 1) ^ ((a >> 16) & 1) ^ ((a >> 17) & 1) ^ ((a >> 18) & 1) ^ ((a >> 19) & 1) ^
         ((a >> 31) & 1) ^ ((a >> 32) & 1) ^ ((a >> 33) & 1) ^ ((a >> 34) & 1) ^ ((a >> 35) & 1) ^
         ((a >> 36) & 1) ^ ((a >> 37) & 1) ^ ((a >> 50) & 1) ^ ((a >> 51) & 1) ^ ((a >> 52) & 1) ^
         ((a >> 53) & 1) ^ ((a >> 54) & 1) ^ ((a >> 55) & 1) ^ ((a >> 61) & 1) ^ ((a >> 62) & 1) ^
         ((a >> 63) & 1));
    uint8_t ecc_bit_5 =
        (((a >> 20) & 1) ^ ((a >> 21) & 1) ^ ((a >> 22) & 1) ^ ((a >> 23) & 1) ^ ((a >> 24) & 1) ^
         ((a >> 25) & 1) ^ ((a >> 26) & 1) ^ ((a >> 27) & 1) ^ ((a >> 28) & 1) ^ ((a >> 29) & 1) ^
         ((a >> 30) & 1) ^ ((a >> 31) & 1) ^ ((a >> 32) & 1) ^ ((a >> 33) & 1) ^ ((a >> 34) & 1) ^
         ((a >> 35) & 1) ^ ((a >> 36) & 1) ^ ((a >> 37) & 1) ^ ((a >> 56) & 1) ^ ((a >> 57) & 1) ^
         ((a >> 58) & 1) ^ ((a >> 59) & 1) ^ ((a >> 60) & 1) ^ ((a >> 61) & 1) ^ ((a >> 62) & 1) ^
         ((a >> 63) & 1));
    uint8_t ecc_bit_6 =
        (((a >> 38) & 1) ^ ((a >> 39) & 1) ^ ((a >> 40) & 1) ^ ((a >> 41) & 1) ^ ((a >> 42) & 1) ^
         ((a >> 43) & 1) ^ ((a >> 44) & 1) ^ ((a >> 45) & 1) ^ ((a >> 46) & 1) ^ ((a >> 47) & 1) ^
         ((a >> 48) & 1) ^ ((a >> 49) & 1) ^ ((a >> 50) & 1) ^ ((a >> 51) & 1) ^ ((a >> 52) & 1) ^
         ((a >> 53) & 1) ^ ((a >> 54) & 1) ^ ((a >> 55) & 1) ^ ((a >> 56) & 1) ^ ((a >> 57) & 1) ^
         ((a >> 58) & 1) ^ ((a >> 59) & 1) ^ ((a >> 60) & 1) ^ ((a >> 61) & 1) ^ ((a >> 62) & 1) ^
         ((a >> 63) & 1));
    uint8_t ecc_bit_7 =
        (((a >> 0) & 1) ^ ((a >> 1) & 1) ^ ((a >> 2) & 1) ^ ((a >> 4) & 1) ^ ((a >> 5) & 1) ^
         ((a >> 7) & 1) ^ ((a >> 10) & 1) ^ ((a >> 11) & 1) ^ ((a >> 13) & 1) ^ ((a >> 16) & 1) ^
         ((a >> 20) & 1) ^ ((a >> 21) & 1) ^ ((a >> 23) & 1) ^ ((a >> 26) & 1) ^ ((a >> 31) & 1) ^
         ((a >> 36) & 1) ^ ((a >> 38) & 1) ^ ((a >> 39) & 1) ^ ((a >> 41) & 1) ^ ((a >> 44) & 1) ^
         ((a >> 47) & 1) ^ ((a >> 49) & 1) ^ ((a >> 50) & 1) ^ ((a >> 54) & 1) ^ ((a >> 56) & 1) ^
         ((a >> 62) & 1));
    ecc_bits = (ecc_bit_7 << 7) | (ecc_bit_6 << 6) | (ecc_bit_5 << 5) | (ecc_bit_4 << 4) |
               (ecc_bit_3 << 3) | (ecc_bit_2 << 2) | (ecc_bit_1 << 1) | ecc_bit_0;
    return ecc_bits;
}

ECC_ICacheDRamErrInject()

__STATIC_FORCEINLINE void ECC_ICacheDRamErrInject	(	uint32_t	ecc_code,
		void *	addr
	)

Inject error into I-Cache Data RAM.

This function injects an error into the I-Cache Data RAM at the specified address with the given ECC code.

Parameters

[in]	ecc_code	ECC code to inject
[in]	addr	Address where error should be injected

Definition at line 332 of file core_feature_ecc.h.

{
    /* Write ecc_code into mecc_code csr also clear all error status */
    __RV_CSR_WRITE(CSR_MECC_CODE, ecc_code);
    MInvalICacheLine((unsigned long)addr);
    __RWMB();
    __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_DRAM_ECC_INJ_EN);
    MLockICacheLine((unsigned long)addr);
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_IC_DRAM_ECC_INJ_EN);
    __RWMB();
}

References __RV_CSR_CLEAR, __RV_CSR_SET, __RV_CSR_WRITE, __RWMB, CSR_MCACHE_CTL, CSR_MECC_CODE, MCACHE_CTL_IC_DRAM_ECC_INJ_EN, MInvalICacheLine(), and MLockICacheLine().

ECC_ICacheErrRestore()

__STATIC_FORCEINLINE void ECC_ICacheErrRestore

(

void *

addr

)

Restore I-Cache error at specified address.

This function restores the correct ECC code for the I-Cache line at the specified address.

Parameters

[in]

addr

Address to restore

Definition at line 350 of file core_feature_ecc.h.

{
    /* Re-lock cache to restore the correct ecc code */
    MInvalICacheLine((unsigned long)addr);
    MLockICacheLine((unsigned long)addr);
}

References MInvalICacheLine(), and MLockICacheLine().

ECC_ICacheTRamErrInject()

__STATIC_FORCEINLINE void ECC_ICacheTRamErrInject	(	uint32_t	ecc_code,
		void *	addr
	)

Inject error into I-Cache Tag RAM.

This function injects an error into the I-Cache Tag RAM at the specified address with the given ECC code.

Parameters

[in]	ecc_code	ECC code to inject
[in]	addr	Address where error should be injected

Definition at line 312 of file core_feature_ecc.h.

{
    /* Write ecc_code into mecc_code csr also clear all error status */
    __RV_CSR_WRITE(CSR_MECC_CODE, ecc_code);
    MInvalICacheLine((unsigned long)addr);
    __RWMB();
    __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_TRAM_ECC_INJ_EN);
    MLockICacheLine((unsigned long)addr);
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_IC_TRAM_ECC_INJ_EN);
    __RWMB();
}

References __RV_CSR_CLEAR, __RV_CSR_SET, __RV_CSR_WRITE, __RWMB, CSR_MCACHE_CTL, CSR_MECC_CODE, MCACHE_CTL_IC_TRAM_ECC_INJ_EN, MInvalICacheLine(), and MLockICacheLine().

ECC_ILMErrInject()

__STATIC_FORCEINLINE void ECC_ILMErrInject	(	uint32_t	ecc_code,
		void *	addr
	)

Inject error into ILM.

This function injects an error into the ILM at the specified address with the given ECC code.

Parameters

[in]	ecc_code	ECC code to inject
[in]	addr	Address where error should be injected

Definition at line 506 of file core_feature_ecc.h.

{
    /* Write ecc_code into mecc_code csr also clear all error status */
    __RV_CSR_WRITE(CSR_MECC_CODE, ecc_code);
    ECC_DisableILMECCCheck();
    uint32_t val = __LW(addr);
    __RWMB(); // make sure setting the ECC_INJ_EN bit before any other memory access
    __RV_CSR_SET(CSR_MILM_CTL, MILM_CTL_ILM_ECC_INJ_EN);
    __SW(addr, val);
    __RWMB(); // make sure the error injection is finished
    __RV_CSR_CLEAR(CSR_MILM_CTL, MILM_CTL_ILM_ECC_INJ_EN);
    __RWMB(); // make sure clearing the ECC_INJ_EN bit before any other memory access
    ECC_EnableILMECCCheck();
}

References __LW(), __RV_CSR_CLEAR, __RV_CSR_SET, __RV_CSR_WRITE, __RWMB, __SW(), CSR_MECC_CODE, CSR_MILM_CTL, ECC_DisableILMECCCheck(), ECC_EnableILMECCCheck(), and MILM_CTL_ILM_ECC_INJ_EN.

ECC_ILMErrRestore()

__STATIC_FORCEINLINE void ECC_ILMErrRestore

(

void *

addr

)

Restore ILM error at specified address.

This function restores the correct ECC code for the ILM at the specified address.

Parameters

[in]

addr

Address to restore

Definition at line 527 of file core_feature_ecc.h.

{
    ECC_DisableILMECCCheck();
    __RWMB();
    __SW(addr, __LW(addr));
    __RWMB();
    ECC_EnableILMECCCheck();
}

References __LW(), __RWMB, __SW(), ECC_DisableILMECCCheck(), and ECC_EnableILMECCCheck().

ECC_IsAnyDoubleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsAnyDoubleBitErrorOccured

(

void

)

Check if any double-bit error has occurred.

This function checks if any double-bit error has occurred by reading the machine ECC code CSR.

Returns

1 if any double-bit error has occurred, 0 otherwise

Definition at line 809 of file core_feature_ecc.h.

{
    CSR_MECC_CODE_Type mecc_code;
    mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
    return mecc_code.b.ramid;
}

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, and CSR_MECCCODE_Type::ramid.

ECC_IsAnySingleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsAnySingleBitErrorOccured

(

void

)

Check if any single-bit error has occurred.

This function checks if any single-bit error has occurred by reading the machine ECC code CSR.

Returns

1 if any single-bit error has occurred, 0 otherwise

Definition at line 665 of file core_feature_ecc.h.

{
    CSR_MECC_CODE_Type mecc_code;
    mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
    return mecc_code.b.sramid;
}

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, and CSR_MECCCODE_Type::sramid.

ECC_IsDCacheDoubleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsDCacheDoubleBitErrorOccured

(

void

)

Check if D-Cache double-bit error has occurred.

This function checks if a double-bit error has occurred in the D-Cache.

Returns

1 if D-Cache double-bit error has occurred, 0 otherwise

Definition at line 835 of file core_feature_ecc.h.

{
    CSR_MECC_CODE_Type mecc_code;
    mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
    return mecc_code.b.ramid & ECC_ERROR_RAMID_MASK_DCACHE;
}

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_DCACHE, and CSR_MECCCODE_Type::ramid.

ECC_IsDCacheSingleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsDCacheSingleBitErrorOccured

(

void

)

Check if D-Cache single-bit error has occurred.

This function checks if a single-bit error has occurred in the D-Cache.

Returns

1 if D-Cache single-bit error has occurred, 0 otherwise

Definition at line 691 of file core_feature_ecc.h.

{
    CSR_MECC_CODE_Type mecc_code;
    mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
    return mecc_code.b.sramid & ECC_ERROR_RAMID_MASK_DCACHE;
}

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_DCACHE, and CSR_MECCCODE_Type::sramid.

ECC_IsDCacheSupportECC()

__STATIC_FORCEINLINE int32_t ECC_IsDCacheSupportECC

(

void

)

Check if D-Cache supports ECC.

This function checks if both D-Cache and ECC are supported in the core.

Returns

1 if D-Cache supports ECC, 0 otherwise

Definition at line 101 of file core_feature_ecc.h.

{
    CSR_MCFGINFO_Type mcfginfo;
    CSR_MDCFGINFO_Type mdcfginfo;
    mcfginfo.d = __RV_CSR_READ(CSR_MCFG_INFO);
    mdcfginfo.d = __RV_CSR_READ(CSR_MDCFG_INFO);
    return mcfginfo.b.dcache && mdcfginfo.b.ecc;
}

References __RV_CSR_READ, CSR_MCFGINFO_Type::b, CSR_MDCFGINFO_Type::b, CSR_MCFG_INFO, CSR_MDCFG_INFO, CSR_MCFGINFO_Type::d, CSR_MDCFGINFO_Type::d, CSR_MCFGINFO_Type::dcache, and CSR_MDCFGINFO_Type::ecc.

ECC_IsDLMDoubleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsDLMDoubleBitErrorOccured

(

void

)

Check if DLM double-bit error has occurred.

This function checks if a double-bit error has occurred in the DLM.

Returns

1 if DLM double-bit error has occurred, 0 otherwise

Definition at line 874 of file core_feature_ecc.h.

{
    CSR_MECC_CODE_Type mecc_code;
    mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
    return mecc_code.b.ramid & ECC_ERROR_RAMID_MASK_DLM;
}

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_DLM, and CSR_MECCCODE_Type::ramid.

ECC_IsDLMSingleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsDLMSingleBitErrorOccured

(

void

)

Check if DLM single-bit error has occurred.

This function checks if a single-bit error has occurred in the DLM.

Returns

1 if DLM single-bit error has occurred, 0 otherwise

Definition at line 730 of file core_feature_ecc.h.

{
    CSR_MECC_CODE_Type mecc_code;
    mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
    return mecc_code.b.sramid & ECC_ERROR_RAMID_MASK_DLM;
}

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_DLM, and CSR_MECCCODE_Type::sramid.

ECC_IsDLMSupportECC()

__STATIC_FORCEINLINE int32_t ECC_IsDLMSupportECC

(

void

)

Check if DLM supports ECC.

This function checks if both DLM and ECC are supported in the core.

Returns

1 if DLM supports ECC, 0 otherwise

Definition at line 148 of file core_feature_ecc.h.

{
    CSR_MCFGINFO_Type mcfginfo;
    CSR_MDCFGINFO_Type mdcfginfo;
    mcfginfo.d = __RV_CSR_READ(CSR_MCFG_INFO);
    mdcfginfo.d = __RV_CSR_READ(CSR_MDCFG_INFO);
    return mcfginfo.b.dlm && mdcfginfo.b.lm_ecc;
}

References __RV_CSR_READ, CSR_MCFGINFO_Type::b, CSR_MDCFGINFO_Type::b, CSR_MCFG_INFO, CSR_MDCFG_INFO, CSR_MCFGINFO_Type::d, CSR_MDCFGINFO_Type::d, CSR_MCFGINFO_Type::dlm, and CSR_MDCFGINFO_Type::lm_ecc.

ECC_IsGlobalSupportECC()

__STATIC_FORCEINLINE int32_t ECC_IsGlobalSupportECC

(

void

)

Check if the core globally supports ECC.

This function reads the machine configuration info CSR and checks if ECC is supported globally in the core.

Returns

1 if ECC is globally supported, 0 otherwise

Definition at line 73 of file core_feature_ecc.h.

{
    CSR_MCFGINFO_Type mcfginfo;
    mcfginfo.d = __RV_CSR_READ(CSR_MCFG_INFO);
    return mcfginfo.b.ecc;
}

References __RV_CSR_READ, CSR_MCFGINFO_Type::b, CSR_MCFG_INFO, CSR_MCFGINFO_Type::d, and CSR_MCFGINFO_Type::ecc.

ECC_IsICacheDoubleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsICacheDoubleBitErrorOccured

(

void

)

Check if I-Cache double-bit error has occurred.

This function checks if a double-bit error has occurred in the I-Cache.

Returns

1 if I-Cache double-bit error has occurred, 0 otherwise

Definition at line 822 of file core_feature_ecc.h.

{
    CSR_MECC_CODE_Type mecc_code;
    mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
    return mecc_code.b.ramid & ECC_ERROR_RAMID_MASK_ICACHE;
}

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_ICACHE, and CSR_MECCCODE_Type::ramid.

ECC_IsICacheSingleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsICacheSingleBitErrorOccured

(

void

)

Check if I-Cache single-bit error has occurred.

This function checks if a single-bit error has occurred in the I-Cache.

Returns

1 if I-Cache single-bit error has occurred, 0 otherwise

Definition at line 678 of file core_feature_ecc.h.

{
    CSR_MECC_CODE_Type mecc_code;
    mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
    return mecc_code.b.sramid & ECC_ERROR_RAMID_MASK_ICACHE;
}

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_ICACHE, and CSR_MECCCODE_Type::sramid.

ECC_IsICacheSupportECC()

__STATIC_FORCEINLINE int32_t ECC_IsICacheSupportECC

(

void

)

Check if I-Cache supports ECC.

This function checks if both I-Cache and ECC are supported in the core.

Returns

1 if I-Cache supports ECC, 0 otherwise

Definition at line 86 of file core_feature_ecc.h.

{
    CSR_MCFGINFO_Type mcfginfo;
    CSR_MICFGINFO_Type micfginfo;
    mcfginfo.d = __RV_CSR_READ(CSR_MCFG_INFO);
    micfginfo.d = __RV_CSR_READ(CSR_MICFG_INFO);
    return mcfginfo.b.icache && micfginfo.b.ecc;
}

References __RV_CSR_READ, CSR_MCFGINFO_Type::b, CSR_MICFGINFO_Type::b, CSR_MCFG_INFO, CSR_MICFG_INFO, CSR_MCFGINFO_Type::d, CSR_MICFGINFO_Type::d, CSR_MICFGINFO_Type::ecc, and CSR_MCFGINFO_Type::icache.

ECC_IsILMDoubleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsILMDoubleBitErrorOccured

(

void

)

Check if ILM double-bit error has occurred.

This function checks if a double-bit error has occurred in the ILM.

Returns

1 if ILM double-bit error has occurred, 0 otherwise

Definition at line 861 of file core_feature_ecc.h.

{
    CSR_MECC_CODE_Type mecc_code;
    mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
    return mecc_code.b.ramid & ECC_ERROR_RAMID_MASK_ILM;
}

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_ILM, and CSR_MECCCODE_Type::ramid.

ECC_IsILMSingleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsILMSingleBitErrorOccured

(

void

)

Check if ILM single-bit error has occurred.

This function checks if a single-bit error has occurred in the ILM.

Returns

1 if ILM single-bit error has occurred, 0 otherwise

Definition at line 717 of file core_feature_ecc.h.

{
    CSR_MECC_CODE_Type mecc_code;
    mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
    return mecc_code.b.sramid & ECC_ERROR_RAMID_MASK_ILM;
}

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_ILM, and CSR_MECCCODE_Type::sramid.

ECC_IsILMSupportECC()

__STATIC_FORCEINLINE int32_t ECC_IsILMSupportECC

(

void

)

Check if ILM supports ECC.

This function checks if both ILM and ECC are supported in the core.

Returns

1 if ILM supports ECC, 0 otherwise

Definition at line 133 of file core_feature_ecc.h.

{
    CSR_MCFGINFO_Type mcfginfo;
    CSR_MICFGINFO_Type micfginfo;
    mcfginfo.d = __RV_CSR_READ(CSR_MCFG_INFO);
    micfginfo.d = __RV_CSR_READ(CSR_MICFG_INFO);
    return mcfginfo.b.ilm && micfginfo.b.lm_ecc;
}

References __RV_CSR_READ, CSR_MCFGINFO_Type::b, CSR_MICFGINFO_Type::b, CSR_MCFG_INFO, CSR_MICFG_INFO, CSR_MCFGINFO_Type::d, CSR_MICFGINFO_Type::d, CSR_MCFGINFO_Type::ilm, and CSR_MICFGINFO_Type::lm_ecc.

ECC_IsTLBDoubleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsTLBDoubleBitErrorOccured

(

void

)

Check if TLB double-bit error has occurred.

This function checks if a double-bit error has occurred in the TLB.

Returns

1 if TLB double-bit error has occurred, 0 otherwise

Definition at line 848 of file core_feature_ecc.h.

{
    CSR_MECC_CODE_Type mecc_code;
    mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
    return mecc_code.b.ramid & ECC_ERROR_RAMID_MASK_DLM;
}

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_DLM, and CSR_MECCCODE_Type::ramid.

ECC_IsTLBSingleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsTLBSingleBitErrorOccured

(

void

)

Check if TLB single-bit error has occurred.

This function checks if a single-bit error has occurred in the TLB.

Returns

1 if TLB single-bit error has occurred, 0 otherwise

Definition at line 704 of file core_feature_ecc.h.

{
    CSR_MECC_CODE_Type mecc_code;
    mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
    return mecc_code.b.sramid & ECC_ERROR_RAMID_MASK_DLM;
}

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_DLM, and CSR_MECCCODE_Type::sramid.

ECC_IsTLBSupportECC()

__STATIC_FORCEINLINE int32_t ECC_IsTLBSupportECC

(

void

)

Check if TLB supports ECC.

This function checks if both PLIC and TLB ECC are supported in the core. Note: TLB is only present with MMU, and when PLIC is present, MMU will be present.

Returns

1 if TLB supports ECC, 0 otherwise

Definition at line 117 of file core_feature_ecc.h.

{
    CSR_MCFGINFO_Type mcfginfo;
    CSR_MTLBCFGINFO_Type mtlbcfginfo;
    mcfginfo.d = __RV_CSR_READ(CSR_MCFG_INFO);
    mtlbcfginfo.d = __RV_CSR_READ(CSR_MTLBCFG_INFO);
    /* TLB only present with MMU, when PLIC present MMU will present */
    return mcfginfo.b.plic && mtlbcfginfo.b.ecc;
}

References __RV_CSR_READ, CSR_MCFGINFO_Type::b, CSR_MTLBCFGINFO_Type::b, CSR_MCFG_INFO, CSR_MTLBCFG_INFO, CSR_MCFGINFO_Type::d, CSR_MTLBCFGINFO_Type::d, CSR_MTLBCFGINFO_Type::ecc, and CSR_MCFGINFO_Type::plic.

ECC_IsXorErrorInjectMode()

__STATIC_FORCEINLINE int32_t ECC_IsXorErrorInjectMode

(

void

)

Check if XOR error injection mode is supported.

This function reads the machine ECC code CSR and checks if error injection mode is suppported.

Returns

1 if XOR error injection mode is enabled, 0 otherwise

Definition at line 163 of file core_feature_ecc.h.

{
    CSR_MECC_CODE_Type mecc_code;
    mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
    return mecc_code.b.ecc_inj_mode;
}

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, and CSR_MECCCODE_Type::ecc_inj_mode.