Intrinsic Functions for CPU Intructions

Functions that generate RISC-V CPU instructions. More...

Enumerations
enum	WFI_SleepMode_Type {   WFI_SHALLOW_SLEEP = 0 ,   WFI_DEEP_SLEEP = 1 }
	WFI Sleep Mode enumeration. More...

Functions
__STATIC_FORCEINLINE void	__NOP (void)
	NOP Instruction. More...
__STATIC_FORCEINLINE void	__WFI (void)
	Wait For Interrupt. More...
__STATIC_FORCEINLINE void	__WFE (void)
	Wait For Event. More...
__STATIC_FORCEINLINE void	__EBREAK (void)
	Breakpoint Instruction. More...
__STATIC_FORCEINLINE void	__ECALL (void)
	Environment Call Instruction. More...
__STATIC_FORCEINLINE void	__set_wfi_sleepmode (WFI_SleepMode_Type mode)
	Set Sleep mode of WFI. More...
__STATIC_FORCEINLINE void	__TXEVT (void)
	Send TX Event. More...
__STATIC_FORCEINLINE void	__enable_mcycle_counter (void)
	Enable MCYCLE counter. More...
__STATIC_FORCEINLINE void	__disable_mcycle_counter (void)
	Disable MCYCLE counter. More...
__STATIC_FORCEINLINE void	__enable_minstret_counter (void)
	Enable MINSTRET counter. More...
__STATIC_FORCEINLINE void	__disable_minstret_counter (void)
	Disable MINSTRET counter. More...
__STATIC_FORCEINLINE void	__enable_mhpm_counter (unsigned long idx)
	Enable selected hardware performance monitor counter. More...
__STATIC_FORCEINLINE void	__disable_mhpm_counter (unsigned long idx)
	Disable selected hardware performance monitor counter. More...
__STATIC_FORCEINLINE void	__enable_mhpm_counters (unsigned long mask)
	Enable hardware performance counters with mask. More...
__STATIC_FORCEINLINE void	__disable_mhpm_counters (unsigned long mask)
	Disable hardware performance counters with mask. More...
__STATIC_FORCEINLINE void	__enable_all_counter (void)
	Enable all MCYCLE & MINSTRET & MHPMCOUNTER counter. More...
__STATIC_FORCEINLINE void	__disable_all_counter (void)
	Disable all MCYCLE & MINSTRET & MHPMCOUNTER counter. More...
__STATIC_INLINE void	__set_hpm_event (unsigned long idx, unsigned long event)
	Set event for selected high performance monitor event. More...
__STATIC_INLINE unsigned long	__get_hpm_event (unsigned long idx)
	Get event for selected high performance monitor event. More...
__STATIC_INLINE void	__set_hpm_counter (unsigned long idx, uint64_t value)
	Set value for selected high performance monitor counter. More...
__STATIC_INLINE uint64_t	__get_hpm_counter (unsigned long idx)
	Get value of selected high performance monitor counter. More...
__STATIC_INLINE unsigned long	__read_hpm_counter (unsigned long idx)
	Get value of selected high performance monitor counter. More...
__STATIC_FORCEINLINE void	__set_medeleg (unsigned long mask)
	Set exceptions delegation to S mode. More...
__STATIC_FORCEINLINE void	__set_mideleg (unsigned long mask)
	Set interrupt delegation to S mode. More...
__STATIC_FORCEINLINE uint8_t	__LB (volatile void *addr)
	Load 8bit value from address (8 bit) More...
__STATIC_FORCEINLINE uint16_t	__LH (volatile void *addr)
	Load 16bit value from address (16 bit) More...
__STATIC_FORCEINLINE uint32_t	__LW (volatile void *addr)
	Load 32bit value from address (32 bit) More...
__STATIC_FORCEINLINE void	__SB (volatile void *addr, uint8_t val)
	Write 8bit value to address (8 bit) More...
__STATIC_FORCEINLINE void	__SH (volatile void *addr, uint16_t val)
	Write 16bit value to address (16 bit) More...
__STATIC_FORCEINLINE void	__SW (volatile void *addr, uint32_t val)
	Write 32bit value to address (32 bit) More...
__STATIC_INLINE uint32_t	__CAS_W (volatile uint32_t *addr, uint32_t oldval, uint32_t newval)
	Compare and Swap 32bit value using LR and SC. More...
__STATIC_FORCEINLINE uint32_t	__AMOSWAP_W (volatile uint32_t *addr, uint32_t newval)
	Atomic Swap 32bit value into memory. More...
__STATIC_FORCEINLINE int32_t	__AMOADD_W (volatile int32_t *addr, int32_t value)
	Atomic Add with 32bit value. More...
__STATIC_FORCEINLINE int32_t	__AMOAND_W (volatile int32_t *addr, int32_t value)
	Atomic And with 32bit value. More...
__STATIC_FORCEINLINE int32_t	__AMOOR_W (volatile int32_t *addr, int32_t value)
	Atomic OR with 32bit value. More...
__STATIC_FORCEINLINE int32_t	__AMOXOR_W (volatile int32_t *addr, int32_t value)
	Atomic XOR with 32bit value. More...
__STATIC_FORCEINLINE uint32_t	__AMOMAXU_W (volatile uint32_t *addr, uint32_t value)
	Atomic unsigned MAX with 32bit value. More...
__STATIC_FORCEINLINE int32_t	__AMOMAX_W (volatile int32_t *addr, int32_t value)
	Atomic signed MAX with 32bit value. More...
__STATIC_FORCEINLINE uint32_t	__AMOMINU_W (volatile uint32_t *addr, uint32_t value)
	Atomic unsigned MIN with 32bit value. More...
__STATIC_FORCEINLINE int32_t	__AMOMIN_W (volatile int32_t *addr, int32_t value)
	Atomic signed MIN with 32bit value. More...
__STATIC_FORCEINLINE void	__enable_ic_prefetch (void)
	Enable ICache prefetch. More...
__STATIC_FORCEINLINE void	__disable_ic_prefetch (void)
	Disable ICache prefetch. More...
__STATIC_FORCEINLINE void	__enable_ic_cmo_prefetch (void)
	Enable ICache CMO prefetch. More...
__STATIC_FORCEINLINE void	__disable_ic_cmo_prefetch (void)
	Disable ICache CMO prefetch. More...
__STATIC_FORCEINLINE void	__enable_dc_cmo_prefetch (void)
	Enable DCache CMO prefetch. More...
__STATIC_FORCEINLINE void	__disable_dc_cmo_prefetch (void)
	Disable DCache CMO prefetch. More...
__STATIC_FORCEINLINE void	__cmo_prefetch_i (const void *addr)
	Instruction prefetch operation. More...
__STATIC_FORCEINLINE void	__cmo_prefetch_r (const void *addr)
	Read prefetch operation. More...
__STATIC_FORCEINLINE void	__cmo_prefetch_w (const void *addr)
	Write prefetch operation. More...

Detailed Description

Functions that generate RISC-V CPU instructions.

The following functions generate specified RISC-V instructions that cannot be directly accessed by compiler.

Enumeration Type Documentation

WFI_SleepMode_Type

enum WFI_SleepMode_Type

WFI Sleep Mode enumeration.

Enumerator
WFI_SHALLOW_SLEEP	Shallow sleep mode, the core_clk will poweroff.
WFI_DEEP_SLEEP	Deep sleep mode, the core_clk and core_ano_clk will poweroff.

Definition at line 1568 of file core_feature_base.h.

                           {
    WFI_SHALLOW_SLEEP = 0,      
    WFI_DEEP_SLEEP = 1          
} WFI_SleepMode_Type;

Function Documentation

__AMOADD_W()

__STATIC_FORCEINLINE int32_t __AMOADD_W	(	volatile int32_t *	addr,
		int32_t	value
	)

Atomic Add with 32bit value.

Atomically ADD 32bit value with value in memory using amoadd.d.

Parameters

[in]	addr	Address pointer to data, address need to be 4byte aligned
[in]	value	value to be ADDed

Returns

return memory value + add value

Definition at line 2357 of file core_feature_base.h.

{
    int32_t result;
 
    __ASM volatile ("amoadd.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}

References __ASM.

__AMOAND_W()

__STATIC_FORCEINLINE int32_t __AMOAND_W	(	volatile int32_t *	addr,
		int32_t	value
	)

Atomic And with 32bit value.

Atomically AND 32bit value with value in memory using amoand.d.

Parameters

[in]	addr	Address pointer to data, address need to be 4byte aligned
[in]	value	value to be ANDed

Returns

return memory value & and value

Definition at line 2373 of file core_feature_base.h.

{
    int32_t result;
 
    __ASM volatile ("amoand.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}

References __ASM.

__AMOMAX_W()

__STATIC_FORCEINLINE int32_t __AMOMAX_W	(	volatile int32_t *	addr,
		int32_t	value
	)

Atomic signed MAX with 32bit value.

Atomically signed max compare 32bit value with value in memory using amomax.d.

Parameters

[in]	addr	Address pointer to data, address need to be 4byte aligned
[in]	value	value to be compared

Returns

the bigger value

Definition at line 2437 of file core_feature_base.h.

{
    int32_t result;
 
    __ASM volatile ("amomax.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}

References __ASM.

__AMOMAXU_W()

__STATIC_FORCEINLINE uint32_t __AMOMAXU_W	(	volatile uint32_t *	addr,
		uint32_t	value
	)

Atomic unsigned MAX with 32bit value.

Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.

Parameters

[in]	addr	Address pointer to data, address need to be 4byte aligned
[in]	value	value to be compared

Returns

return the bigger value

Definition at line 2421 of file core_feature_base.h.

{
    uint32_t result;
 
    __ASM volatile ("amomaxu.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}

References __ASM.

__AMOMIN_W()

__STATIC_FORCEINLINE int32_t __AMOMIN_W	(	volatile int32_t *	addr,
		int32_t	value
	)

Atomic signed MIN with 32bit value.

Atomically signed min compare 32bit value with value in memory using amomin.d.

Parameters

[in]	addr	Address pointer to data, address need to be 4byte aligned
[in]	value	value to be compared

Returns

the smaller value

Definition at line 2469 of file core_feature_base.h.

{
    int32_t result;
 
    __ASM volatile ("amomin.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}

References __ASM.

__AMOMINU_W()

__STATIC_FORCEINLINE uint32_t __AMOMINU_W	(	volatile uint32_t *	addr,
		uint32_t	value
	)

Atomic unsigned MIN with 32bit value.

Atomically unsigned min compare 32bit value with value in memory using amominu.d.

Parameters

[in]	addr	Address pointer to data, address need to be 4byte aligned
[in]	value	value to be compared

Returns

the smaller value

Definition at line 2453 of file core_feature_base.h.

{
    uint32_t result;
 
    __ASM volatile ("amominu.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}

References __ASM.

__AMOOR_W()

__STATIC_FORCEINLINE int32_t __AMOOR_W	(	volatile int32_t *	addr,
		int32_t	value
	)

Atomic OR with 32bit value.

Atomically OR 32bit value with value in memory using amoor.d.

Parameters

[in]	addr	Address pointer to data, address need to be 4byte aligned
[in]	value	value to be ORed

Returns

return memory value | and value

Definition at line 2389 of file core_feature_base.h.

{
    int32_t result;
 
    __ASM volatile ("amoor.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}

References __ASM.

__AMOSWAP_W()

__STATIC_FORCEINLINE uint32_t __AMOSWAP_W	(	volatile uint32_t *	addr,
		uint32_t	newval
	)

Atomic Swap 32bit value into memory.

Atomically swap new 32bit value into memory using amoswap.d.

Parameters

[in]	addr	Address pointer to data, address need to be 4byte aligned
[in]	newval	New value to be stored into the address

Returns

return the original value in memory

Definition at line 2341 of file core_feature_base.h.

{
    uint32_t result;
 
    __ASM volatile ("amoswap.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
    return result;
}

References __ASM.

__AMOXOR_W()

__STATIC_FORCEINLINE int32_t __AMOXOR_W	(	volatile int32_t *	addr,
		int32_t	value
	)

Atomic XOR with 32bit value.

Atomically XOR 32bit value with value in memory using amoxor.d.

Parameters

[in]	addr	Address pointer to data, address need to be 4byte aligned
[in]	value	value to be XORed

Returns

return memory value ^ and value

Definition at line 2405 of file core_feature_base.h.

{
    int32_t result;
 
    __ASM volatile ("amoxor.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}

References __ASM.

__CAS_W()

__STATIC_INLINE uint32_t __CAS_W	(	volatile uint32_t *	addr,
		uint32_t	oldval,
		uint32_t	newval
	)

Compare and Swap 32bit value using LR and SC.

Compare old value with memory, if identical, store new value in memory. Return the initial value in memory. Success is indicated by comparing return value with OLD. memory address, return 0 if successful, otherwise return !0

Parameters

[in]	addr	Address pointer to data, address need to be 4byte aligned
[in]	oldval	Old value of the data in address
[in]	newval	New value to be stored into the address

Returns

return the initial value in memory

Definition at line 2317 of file core_feature_base.h.

{
    uint32_t result;
    uint32_t rc;
 
    __ASM volatile (                                \
            "0:     lr.w %0, %2      \n"            \
            "       bne  %0, %z3, 1f \n"            \
            "       sc.w %1, %z4, %2 \n"            \
            "       bnez %1, 0b      \n"            \
            "1:\n"                                  \
            : "=&r"(result), "=&r"(rc), "+A"(*addr) \
            : "r"(oldval), "r"(newval)              \
            : "memory");
    return result;
}

References __ASM.

__cmo_prefetch_i()

__STATIC_FORCEINLINE void __cmo_prefetch_i

(

const void *

addr

)

Instruction prefetch operation.

Performs an instruction prefetch operation for the specified address using the RISC-V prefetch.i instruction.

Parameters

[in]

addr

Address to prefetch

Remarks

Before calling this function, ensure that the hardware supports CMO prefetch and that the code is compiled with the _zicbop extension enabled. Here is a code example to check if CMO prefetch is supported:

if (IINFO_IsCMOPrefetchSupported()) {
    __cmo_prefetch_i(func);
}

See also

• IINFO_IsCMOPrefetchSupported

Definition at line 2731 of file core_feature_base.h.

{
    __ASM volatile ("prefetch.i 0(%0)" : : "r" (addr) : "memory");
}

References __ASM.

__cmo_prefetch_r()

__STATIC_FORCEINLINE void __cmo_prefetch_r

(

const void *

addr

)

Read prefetch operation.

Performs a read prefetch operation for the specified address using the RISC-V prefetch.r instruction.

Parameters

[in]

addr

Address to prefetch

Remarks

Before calling this function, ensure that the hardware supports CMO prefetch and that the code is compiled with the _zicbop extension enabled. Here is a code example to check if CMO prefetch is supported:

if (IINFO_IsCMOPrefetchSupported()) {
    __cmo_prefetch_r(data);
}

See also

• IINFO_IsCMOPrefetchSupported

Definition at line 2755 of file core_feature_base.h.

{
    __ASM volatile ("prefetch.r 0(%0)" : : "r" (addr) : "memory");
}

References __ASM.

__cmo_prefetch_w()

__STATIC_FORCEINLINE void __cmo_prefetch_w

(

const void *

addr

)

Write prefetch operation.

Performs a write prefetch operation for the specified address using the RISC-V prefetch.w instruction.

Parameters

[in]

addr

Address to prefetch

Remarks

Before calling this function, ensure that the hardware supports CMO prefetch and that the code is compiled with the _zicbop extension enabled. Here is a code example to check if CMO prefetch is supported:

if (IINFO_IsCMOPrefetchSupported()) {
    __cmo_prefetch_w(data);
}

See also

• IINFO_IsCMOPrefetchSupported

Definition at line 2779 of file core_feature_base.h.

{
    __ASM volatile ("prefetch.w 0(%0)" : : "r" (addr) : "memory");
}

References __ASM.

__disable_all_counter()

__STATIC_FORCEINLINE void __disable_all_counter

(

void

)

Disable all MCYCLE & MINSTRET & MHPMCOUNTER counter.

Set all to one to disable all counters, such as cycle, instret, high performance monitor counters

Definition at line 1699 of file core_feature_base.h.

{
    __RV_CSR_SET(CSR_MCOUNTINHIBIT, 0xFFFFFFFF);
}

References __RV_CSR_SET, and CSR_MCOUNTINHIBIT.

__disable_dc_cmo_prefetch()

__STATIC_FORCEINLINE void __disable_dc_cmo_prefetch

(

void

)

Disable DCache CMO prefetch.

Clear the DC_CMO_PF_EN bit in the MCACHE_CTL CSR to disable DCache prefetch.

Definition at line 2707 of file core_feature_base.h.

{
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_DC_CMO_PF_EN);
}

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_DC_CMO_PF_EN.

__disable_ic_cmo_prefetch()

__STATIC_FORCEINLINE void __disable_ic_cmo_prefetch

(

void

)

Disable ICache CMO prefetch.

Clear the IC_CMO_PF_EN bit in the MCACHE_CTL CSR to disable ICache prefetch.

Definition at line 2687 of file core_feature_base.h.

{
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_IC_CMO_PF_EN);
}

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_IC_CMO_PF_EN.

__disable_ic_prefetch()

__STATIC_FORCEINLINE void __disable_ic_prefetch

(

void

)

Disable ICache prefetch.

Clear the IC_PF_EN bit in the MCACHE_CTL CSR to disable ICache prefetch.

Definition at line 2667 of file core_feature_base.h.

{
    __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_IC_PF_EN);
}

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_IC_PF_EN.

__disable_mcycle_counter()

__STATIC_FORCEINLINE void __disable_mcycle_counter

(

void

)

Disable MCYCLE counter.

Set the CY bit of MCOUNTINHIBIT to 1 to disable MCYCLE Counter

Definition at line 1611 of file core_feature_base.h.

{
    __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY);
}

References __RV_CSR_SET, CSR_MCOUNTINHIBIT, and MCOUNTINHIBIT_CY.

__disable_mhpm_counter()

__STATIC_FORCEINLINE void __disable_mhpm_counter

(

unsigned long

idx

)

Disable selected hardware performance monitor counter.

Parameters

[in]

idx

the index of the hardware performance monitor counter

Disable selected hardware performance monitor counter mhpmcounterx.

Definition at line 1653 of file core_feature_base.h.

{
    __RV_CSR_SET(CSR_MCOUNTINHIBIT, (1UL << idx));
}

References __RV_CSR_SET, and CSR_MCOUNTINHIBIT.

__disable_mhpm_counters()

__STATIC_FORCEINLINE void __disable_mhpm_counters

(

unsigned long

mask

)

Disable hardware performance counters with mask.

Parameters

[in]

mask

mask of selected hardware performance monitor counters

Disable mhpmcounterx with mask, only the masked ones will be disabled. mhpmcounter3-mhpmcount31 are for high performance monitor counters.

Definition at line 1677 of file core_feature_base.h.

{
    __RV_CSR_SET(CSR_MCOUNTINHIBIT, mask);
}

References __RV_CSR_SET, and CSR_MCOUNTINHIBIT.

__disable_minstret_counter()

__STATIC_FORCEINLINE void __disable_minstret_counter

(

void

)

Disable MINSTRET counter.

Set the IR bit of MCOUNTINHIBIT to 1 to disable MINSTRET Counter

Definition at line 1631 of file core_feature_base.h.

{
    __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR);
}

References __RV_CSR_SET, CSR_MCOUNTINHIBIT, and MCOUNTINHIBIT_IR.

__EBREAK()

__STATIC_FORCEINLINE void __EBREAK

(

void

)

Breakpoint Instruction.

Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.

Definition at line 1549 of file core_feature_base.h.

{
    __ASM volatile("ebreak");
}

References __ASM.

__ECALL()

__STATIC_FORCEINLINE void __ECALL

(

void

)

Environment Call Instruction.

The ECALL instruction is used to make a service request to the execution environment.

Definition at line 1560 of file core_feature_base.h.

{
    __ASM volatile("ecall");
}

References __ASM.

__enable_all_counter()

__STATIC_FORCEINLINE void __enable_all_counter

(

void

)

Enable all MCYCLE & MINSTRET & MHPMCOUNTER counter.

Clear all to zero to enable all counters, such as cycle, instret, high performance monitor counters

Definition at line 1688 of file core_feature_base.h.

{
    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, 0xFFFFFFFF);
}

References __RV_CSR_CLEAR, and CSR_MCOUNTINHIBIT.

Referenced by __prepare_bench_env().

__enable_dc_cmo_prefetch()

__STATIC_FORCEINLINE void __enable_dc_cmo_prefetch

(

void

)

Enable DCache CMO prefetch.

Set the DC_CMO_PF_EN bit in the MCACHE_CTL CSR to enable DCache prefetch.

Definition at line 2697 of file core_feature_base.h.

{
    __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_DC_CMO_PF_EN);
}

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_DC_CMO_PF_EN.

__enable_ic_cmo_prefetch()

__STATIC_FORCEINLINE void __enable_ic_cmo_prefetch

(

void

)

Enable ICache CMO prefetch.

Set the IC_CMO_PF_EN bit in the MCACHE_CTL CSR to enable ICache prefetch.

Definition at line 2677 of file core_feature_base.h.

{
    __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_CMO_PF_EN);
}

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_IC_CMO_PF_EN.

__enable_ic_prefetch()

__STATIC_FORCEINLINE void __enable_ic_prefetch

(

void

)

Enable ICache prefetch.

Set the IC_PF_EN bit in the MCACHE_CTL CSR to enable ICache prefetch.

Definition at line 2657 of file core_feature_base.h.

{
    __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_PF_EN);
}

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_IC_PF_EN.

__enable_mcycle_counter()

__STATIC_FORCEINLINE void __enable_mcycle_counter

(

void

)

Enable MCYCLE counter.

Clear the CY bit of MCOUNTINHIBIT to 0 to enable MCYCLE Counter

Definition at line 1601 of file core_feature_base.h.

{
    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY);
}

References __RV_CSR_CLEAR, CSR_MCOUNTINHIBIT, and MCOUNTINHIBIT_CY.

__enable_mhpm_counter()

__STATIC_FORCEINLINE void __enable_mhpm_counter

(

unsigned long

idx

)

Enable selected hardware performance monitor counter.

Parameters

[in]

idx

the index of the hardware performance monitor counter

enable selected hardware performance monitor counter mhpmcounterx.

Definition at line 1642 of file core_feature_base.h.

{
    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, (1UL << idx));
}

References __RV_CSR_CLEAR, and CSR_MCOUNTINHIBIT.

__enable_mhpm_counters()

__STATIC_FORCEINLINE void __enable_mhpm_counters

(

unsigned long

mask

)

Enable hardware performance counters with mask.

Parameters

[in]

mask

mask of selected hardware performance monitor counters

enable mhpmcounterx with mask, only the masked ones will be enabled. mhpmcounter3-mhpmcount31 are for high performance monitor counters.

Definition at line 1665 of file core_feature_base.h.

{
    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, mask);
}

References __RV_CSR_CLEAR, and CSR_MCOUNTINHIBIT.

__enable_minstret_counter()

__STATIC_FORCEINLINE void __enable_minstret_counter

(

void

)

Enable MINSTRET counter.

Clear the IR bit of MCOUNTINHIBIT to 0 to enable MINSTRET Counter

Definition at line 1621 of file core_feature_base.h.

{
    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR);
}

References __RV_CSR_CLEAR, CSR_MCOUNTINHIBIT, and MCOUNTINHIBIT_IR.

__get_hpm_counter()

__STATIC_INLINE uint64_t __get_hpm_counter

(

unsigned long

idx

)

Get value of selected high performance monitor counter.

Parameters

[in]

idx

HPMCOUNTERx CSR index(3-31)

Get high performance monitor counter register value

Returns

HPMCOUNTERx Register value

Definition at line 1934 of file core_feature_base.h.

{
    __RWMB();   // Make sure previous memory and io operation finished
#if __RISCV_XLEN == 32
    volatile uint32_t high0, low, high;
    uint64_t full;
 
    switch (idx) {
        case 0: return __get_rv_cycle();
        case 2: return __get_rv_instret();
        case 3: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER3H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER3);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER3H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER3); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 4: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER4H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER4);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER4H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER4); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 5: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER5H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER5);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER5H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER5); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 6: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER6H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER6);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER6H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER6); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 7: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER7H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER7);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER7H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER7); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 8: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER8H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER8);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER8H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER8); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 9: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER9H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER9);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER9H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER9); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 10: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER10H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER10);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER10H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER10); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 11: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER11H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER11);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER11H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER11); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 12: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER12H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER12);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER12H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER12); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 13: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER13H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER13);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER13H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER13); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 14: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER14H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER14);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER14H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER14); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 15: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER15H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER15);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER15H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER15); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 16: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER16H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER16);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER16H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER16); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 17: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER17H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER17);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER17H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER17); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 18: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER18H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER18);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER18H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER18); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 19: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER19H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER19);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER19H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER19); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 20: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER20H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER20);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER20H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER20); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 21: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER21H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER21);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER21H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER21); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 22: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER22H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER22);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER22H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER22); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 23: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER23H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER23);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER23H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER23); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 24: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER24H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER24);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER24H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER24); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 25: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER25H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER25);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER25H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER25); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 26: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER26H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER26);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER26H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER26); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 27: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER27H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER27);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER27H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER27); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 28: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER28H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER28);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER28H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER28); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 29: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER29H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER29);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER29H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER29); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 30: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER30H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER30);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER30H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER30); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 31: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER31H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER31);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER31H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER31); }
            full = (((uint64_t)high) << 32) | low; return full;
 
#elif __RISCV_XLEN == 64
    switch (idx) {
        case 0: return __get_rv_cycle();
        case 2: return __get_rv_instret();
        case 3: return __RV_CSR_READ(CSR_MHPMCOUNTER3);
        case 4: return __RV_CSR_READ(CSR_MHPMCOUNTER4);
        case 5: return __RV_CSR_READ(CSR_MHPMCOUNTER5);
        case 6: return __RV_CSR_READ(CSR_MHPMCOUNTER6);
        case 7: return __RV_CSR_READ(CSR_MHPMCOUNTER7);
        case 8: return __RV_CSR_READ(CSR_MHPMCOUNTER8);
        case 9: return __RV_CSR_READ(CSR_MHPMCOUNTER9);
        case 10: return __RV_CSR_READ(CSR_MHPMCOUNTER10);
        case 11: return __RV_CSR_READ(CSR_MHPMCOUNTER11);
        case 12: return __RV_CSR_READ(CSR_MHPMCOUNTER12);
        case 13: return __RV_CSR_READ(CSR_MHPMCOUNTER13);
        case 14: return __RV_CSR_READ(CSR_MHPMCOUNTER14);
        case 15: return __RV_CSR_READ(CSR_MHPMCOUNTER15);
        case 16: return __RV_CSR_READ(CSR_MHPMCOUNTER16);
        case 17: return __RV_CSR_READ(CSR_MHPMCOUNTER17);
        case 18: return __RV_CSR_READ(CSR_MHPMCOUNTER18);
        case 19: return __RV_CSR_READ(CSR_MHPMCOUNTER19);
        case 20: return __RV_CSR_READ(CSR_MHPMCOUNTER20);
        case 21: return __RV_CSR_READ(CSR_MHPMCOUNTER21);
        case 22: return __RV_CSR_READ(CSR_MHPMCOUNTER22);
        case 23: return __RV_CSR_READ(CSR_MHPMCOUNTER23);
        case 24: return __RV_CSR_READ(CSR_MHPMCOUNTER24);
        case 25: return __RV_CSR_READ(CSR_MHPMCOUNTER25);
        case 26: return __RV_CSR_READ(CSR_MHPMCOUNTER26);
        case 27: return __RV_CSR_READ(CSR_MHPMCOUNTER27);
        case 28: return __RV_CSR_READ(CSR_MHPMCOUNTER28);
        case 29: return __RV_CSR_READ(CSR_MHPMCOUNTER29);
        case 30: return __RV_CSR_READ(CSR_MHPMCOUNTER30);
        case 31: return __RV_CSR_READ(CSR_MHPMCOUNTER31);
 
#else
    switch (idx) {
#endif
        default: return 0;
    }
}

References __get_rv_cycle(), __get_rv_instret(), __RV_CSR_READ, __RWMB, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11, CSR_MHPMCOUNTER11H, CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15, CSR_MHPMCOUNTER15H, CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19, CSR_MHPMCOUNTER19H, CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23, CSR_MHPMCOUNTER23H, CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27, CSR_MHPMCOUNTER27H, CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER3, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31, CSR_MHPMCOUNTER31H, CSR_MHPMCOUNTER3H, CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7, CSR_MHPMCOUNTER7H, CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9, and CSR_MHPMCOUNTER9H.

__get_hpm_event()

__STATIC_INLINE unsigned long __get_hpm_event

(

unsigned long

idx

)

Get event for selected high performance monitor event.

Parameters

[in]	idx	HPMEVENTx CSR index(3-31)
[in]	event	HPMEVENTx Register value to set

Get high performance monitor event register value

Returns

HPMEVENTx Register value

Definition at line 1755 of file core_feature_base.h.

{
    switch (idx) {
        case 3: return __RV_CSR_READ(CSR_MHPMEVENT3);
        case 4: return __RV_CSR_READ(CSR_MHPMEVENT4);
        case 5: return __RV_CSR_READ(CSR_MHPMEVENT5);
        case 6: return __RV_CSR_READ(CSR_MHPMEVENT6);
        case 7: return __RV_CSR_READ(CSR_MHPMEVENT7);
        case 8: return __RV_CSR_READ(CSR_MHPMEVENT8);
        case 9: return __RV_CSR_READ(CSR_MHPMEVENT9);
        case 10: return __RV_CSR_READ(CSR_MHPMEVENT10);
        case 11: return __RV_CSR_READ(CSR_MHPMEVENT11);
        case 12: return __RV_CSR_READ(CSR_MHPMEVENT12);
        case 13: return __RV_CSR_READ(CSR_MHPMEVENT13);
        case 14: return __RV_CSR_READ(CSR_MHPMEVENT14);
        case 15: return __RV_CSR_READ(CSR_MHPMEVENT15);
        case 16: return __RV_CSR_READ(CSR_MHPMEVENT16);
        case 17: return __RV_CSR_READ(CSR_MHPMEVENT17);
        case 18: return __RV_CSR_READ(CSR_MHPMEVENT18);
        case 19: return __RV_CSR_READ(CSR_MHPMEVENT19);
        case 20: return __RV_CSR_READ(CSR_MHPMEVENT20);
        case 21: return __RV_CSR_READ(CSR_MHPMEVENT21);
        case 22: return __RV_CSR_READ(CSR_MHPMEVENT22);
        case 23: return __RV_CSR_READ(CSR_MHPMEVENT23);
        case 24: return __RV_CSR_READ(CSR_MHPMEVENT24);
        case 25: return __RV_CSR_READ(CSR_MHPMEVENT25);
        case 26: return __RV_CSR_READ(CSR_MHPMEVENT26);
        case 27: return __RV_CSR_READ(CSR_MHPMEVENT27);
        case 28: return __RV_CSR_READ(CSR_MHPMEVENT28);
        case 29: return __RV_CSR_READ(CSR_MHPMEVENT29);
        case 30: return __RV_CSR_READ(CSR_MHPMEVENT30);
        case 31: return __RV_CSR_READ(CSR_MHPMEVENT31);
        default: return 0;
    }
}

References __RV_CSR_READ, CSR_MHPMEVENT10, CSR_MHPMEVENT11, CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15, CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19, CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23, CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27, CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT3, CSR_MHPMEVENT30, CSR_MHPMEVENT31, CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7, CSR_MHPMEVENT8, and CSR_MHPMEVENT9.

__LB()

__STATIC_FORCEINLINE uint8_t __LB

(

volatile void *

addr

)

Load 8bit value from address (8 bit)

Load 8 bit value.

Parameters

[in]

addr

Address pointer to data

Returns

value of type uint8_t at (*addr)

Definition at line 2208 of file core_feature_base.h.

{
    uint8_t result;
 
    __ASM volatile ("lb %0, 0(%1)" : "=r" (result) : "r" (addr));
    return result;
}

References __ASM.

__LH()

__STATIC_FORCEINLINE uint16_t __LH

(

volatile void *

addr

)

Load 16bit value from address (16 bit)

Load 16 bit value.

Parameters

[in]

addr

Address pointer to data

Returns

value of type uint16_t at (*addr)

Definition at line 2222 of file core_feature_base.h.

{
    uint16_t result;
 
    __ASM volatile ("lh %0, 0(%1)" : "=r" (result) : "r" (addr));
    return result;
}

References __ASM.

__LW()

__STATIC_FORCEINLINE uint32_t __LW

(

volatile void *

addr

)

Load 32bit value from address (32 bit)

Load 32 bit value.

Parameters

[in]

addr

Address pointer to data

Returns

value of type uint32_t at (*addr)

Definition at line 2236 of file core_feature_base.h.

{
    uint32_t result;
 
    __ASM volatile ("lw %0, 0(%1)" : "=r" (result) : "r" (addr));
    return result;
}

References __ASM.

Referenced by CIDU_GetBroadcastModeStatus(), CIDU_GetClaimStatus(), CIDU_GetCoreNum(), CIDU_GetIntNum(), CIDU_GetSemaphoreStatus(), CIDU_QueryCoreIntSenderMask(), CIDU_SetFirstClaimMode(), ECC_DLMErrInject(), ECC_DLMErrRestore(), ECC_ILMErrInject(), ECC_ILMErrRestore(), SMPCC_CLMErrInject(), SysTimer_GetHartCompareValue(), SysTimer_GetHartMsipValue(), SysTimer_GetHartSsipValue(), and SysTimer_GetLoadValue().

__NOP()

__STATIC_FORCEINLINE void __NOP

(

void

)

NOP Instruction.

No Operation does nothing. This instruction can be used for code alignment purposes.

Definition at line 1508 of file core_feature_base.h.

{
    __ASM volatile("nop");
}

References __ASM.

__read_hpm_counter()

__STATIC_INLINE unsigned long __read_hpm_counter

(

unsigned long

idx

)

Get value of selected high performance monitor counter.

Parameters

[in]

idx

HPMCOUNTERx CSR index(3-31)

Get high performance monitor counter register value without high 32 bits when XLEN=32

Returns

HPMCOUNTERx Register value

Definition at line 2139 of file core_feature_base.h.

{
    switch (idx) {
        case 0: return __read_cycle_csr();
        case 2: return __read_instret_csr();
        case 3: return __RV_CSR_READ(CSR_MHPMCOUNTER3);
        case 4: return __RV_CSR_READ(CSR_MHPMCOUNTER4);
        case 5: return __RV_CSR_READ(CSR_MHPMCOUNTER5);
        case 6: return __RV_CSR_READ(CSR_MHPMCOUNTER6);
        case 7: return __RV_CSR_READ(CSR_MHPMCOUNTER7);
        case 8: return __RV_CSR_READ(CSR_MHPMCOUNTER8);
        case 9: return __RV_CSR_READ(CSR_MHPMCOUNTER9);
        case 10: return __RV_CSR_READ(CSR_MHPMCOUNTER10);
        case 11: return __RV_CSR_READ(CSR_MHPMCOUNTER11);
        case 12: return __RV_CSR_READ(CSR_MHPMCOUNTER12);
        case 13: return __RV_CSR_READ(CSR_MHPMCOUNTER13);
        case 14: return __RV_CSR_READ(CSR_MHPMCOUNTER14);
        case 15: return __RV_CSR_READ(CSR_MHPMCOUNTER15);
        case 16: return __RV_CSR_READ(CSR_MHPMCOUNTER16);
        case 17: return __RV_CSR_READ(CSR_MHPMCOUNTER17);
        case 18: return __RV_CSR_READ(CSR_MHPMCOUNTER18);
        case 19: return __RV_CSR_READ(CSR_MHPMCOUNTER19);
        case 20: return __RV_CSR_READ(CSR_MHPMCOUNTER20);
        case 21: return __RV_CSR_READ(CSR_MHPMCOUNTER21);
        case 22: return __RV_CSR_READ(CSR_MHPMCOUNTER22);
        case 23: return __RV_CSR_READ(CSR_MHPMCOUNTER23);
        case 24: return __RV_CSR_READ(CSR_MHPMCOUNTER24);
        case 25: return __RV_CSR_READ(CSR_MHPMCOUNTER25);
        case 26: return __RV_CSR_READ(CSR_MHPMCOUNTER26);
        case 27: return __RV_CSR_READ(CSR_MHPMCOUNTER27);
        case 28: return __RV_CSR_READ(CSR_MHPMCOUNTER28);
        case 29: return __RV_CSR_READ(CSR_MHPMCOUNTER29);
        case 30: return __RV_CSR_READ(CSR_MHPMCOUNTER30);
        case 31: return __RV_CSR_READ(CSR_MHPMCOUNTER31);
        default: return 0;
    }
}

References __read_cycle_csr(), __read_instret_csr(), __RV_CSR_READ, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11, CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15, CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19, CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23, CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27, CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER3, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31, CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7, CSR_MHPMCOUNTER8, and CSR_MHPMCOUNTER9.

__SB()

__STATIC_FORCEINLINE void __SB	(	volatile void *	addr,
		uint8_t	val
	)

Write 8bit value to address (8 bit)

Write 8 bit value.

Parameters

[in]	addr	Address pointer to data
[in]	val	Value to set

Definition at line 2266 of file core_feature_base.h.

{
    __ASM volatile ("sb %0, 0(%1)" : : "r" (val), "r" (addr));
}

References __ASM.

__set_hpm_counter()

__STATIC_INLINE void __set_hpm_counter	(	unsigned long	idx,
		uint64_t	value
	)

Set value for selected high performance monitor counter.

Parameters

[in]	idx	HPMCOUNTERx CSR index(3-31)
[in]	value	HPMCOUNTERx Register value to set

Set value for high performance monitor couner register

Definition at line 1798 of file core_feature_base.h.

{
    switch (idx) {
#if __RISCV_XLEN == 32
        case 3: __RV_CSR_WRITE(CSR_MHPMCOUNTER3, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER3H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER3, (uint32_t)(value)); break;
        case 4: __RV_CSR_WRITE(CSR_MHPMCOUNTER4, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER4H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER4, (uint32_t)(value)); break;
        case 5: __RV_CSR_WRITE(CSR_MHPMCOUNTER5, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER5H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER5, (uint32_t)(value)); break;
        case 6: __RV_CSR_WRITE(CSR_MHPMCOUNTER6, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER6H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER6, (uint32_t)(value)); break;
        case 7: __RV_CSR_WRITE(CSR_MHPMCOUNTER7, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER7H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER7, (uint32_t)(value)); break;
        case 8: __RV_CSR_WRITE(CSR_MHPMCOUNTER8, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER8H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER8, (uint32_t)(value)); break;
        case 9: __RV_CSR_WRITE(CSR_MHPMCOUNTER9, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER9H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER9, (uint32_t)(value)); break;
        case 10: __RV_CSR_WRITE(CSR_MHPMCOUNTER10, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER10H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER10, (uint32_t)(value)); break;
        case 11: __RV_CSR_WRITE(CSR_MHPMCOUNTER11, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER11H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER11, (uint32_t)(value)); break;
        case 12: __RV_CSR_WRITE(CSR_MHPMCOUNTER12, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER12H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER12, (uint32_t)(value)); break;
        case 13: __RV_CSR_WRITE(CSR_MHPMCOUNTER13, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER13H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER13, (uint32_t)(value)); break;
        case 14: __RV_CSR_WRITE(CSR_MHPMCOUNTER14, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER14H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER14, (uint32_t)(value)); break;
        case 15: __RV_CSR_WRITE(CSR_MHPMCOUNTER15, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER15H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER15, (uint32_t)(value)); break;
        case 16: __RV_CSR_WRITE(CSR_MHPMCOUNTER16, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER16H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER16, (uint32_t)(value)); break;
        case 17: __RV_CSR_WRITE(CSR_MHPMCOUNTER17, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER17H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER17, (uint32_t)(value)); break;
        case 18: __RV_CSR_WRITE(CSR_MHPMCOUNTER18, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER18H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER18, (uint32_t)(value)); break;
        case 19: __RV_CSR_WRITE(CSR_MHPMCOUNTER19, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER19H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER19, (uint32_t)(value)); break;
        case 20: __RV_CSR_WRITE(CSR_MHPMCOUNTER20, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER20H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER20, (uint32_t)(value)); break;
        case 21: __RV_CSR_WRITE(CSR_MHPMCOUNTER21, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER21H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER21, (uint32_t)(value)); break;
        case 22: __RV_CSR_WRITE(CSR_MHPMCOUNTER22, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER22H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER22, (uint32_t)(value)); break;
        case 23: __RV_CSR_WRITE(CSR_MHPMCOUNTER23, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER23H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER23, (uint32_t)(value)); break;
        case 24: __RV_CSR_WRITE(CSR_MHPMCOUNTER24, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER24H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER24, (uint32_t)(value)); break;
        case 25: __RV_CSR_WRITE(CSR_MHPMCOUNTER25, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER25H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER25, (uint32_t)(value)); break;
        case 26: __RV_CSR_WRITE(CSR_MHPMCOUNTER26, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER26H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER26, (uint32_t)(value)); break;
        case 27: __RV_CSR_WRITE(CSR_MHPMCOUNTER27, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER27H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER27, (uint32_t)(value)); break;
        case 28: __RV_CSR_WRITE(CSR_MHPMCOUNTER28, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER28H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER28, (uint32_t)(value)); break;
        case 29: __RV_CSR_WRITE(CSR_MHPMCOUNTER29, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER29H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER29, (uint32_t)(value)); break;
        case 30: __RV_CSR_WRITE(CSR_MHPMCOUNTER30, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER30H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER30, (uint32_t)(value)); break;
        case 31: __RV_CSR_WRITE(CSR_MHPMCOUNTER31, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER31H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER31, (uint32_t)(value)); break;
 
#elif __RISCV_XLEN == 64
        case 3: __RV_CSR_WRITE(CSR_MHPMCOUNTER3, (value)); break;
        case 4: __RV_CSR_WRITE(CSR_MHPMCOUNTER4, (value)); break;
        case 5: __RV_CSR_WRITE(CSR_MHPMCOUNTER5, (value)); break;
        case 6: __RV_CSR_WRITE(CSR_MHPMCOUNTER6, (value)); break;
        case 7: __RV_CSR_WRITE(CSR_MHPMCOUNTER7, (value)); break;
        case 8: __RV_CSR_WRITE(CSR_MHPMCOUNTER8, (value)); break;
        case 9: __RV_CSR_WRITE(CSR_MHPMCOUNTER9, (value)); break;
        case 10: __RV_CSR_WRITE(CSR_MHPMCOUNTER10, (value)); break;
        case 11: __RV_CSR_WRITE(CSR_MHPMCOUNTER11, (value)); break;
        case 12: __RV_CSR_WRITE(CSR_MHPMCOUNTER12, (value)); break;
        case 13: __RV_CSR_WRITE(CSR_MHPMCOUNTER13, (value)); break;
        case 14: __RV_CSR_WRITE(CSR_MHPMCOUNTER14, (value)); break;
        case 15: __RV_CSR_WRITE(CSR_MHPMCOUNTER15, (value)); break;
        case 16: __RV_CSR_WRITE(CSR_MHPMCOUNTER16, (value)); break;
        case 17: __RV_CSR_WRITE(CSR_MHPMCOUNTER17, (value)); break;
        case 18: __RV_CSR_WRITE(CSR_MHPMCOUNTER18, (value)); break;
        case 19: __RV_CSR_WRITE(CSR_MHPMCOUNTER19, (value)); break;
        case 20: __RV_CSR_WRITE(CSR_MHPMCOUNTER20, (value)); break;
        case 21: __RV_CSR_WRITE(CSR_MHPMCOUNTER21, (value)); break;
        case 22: __RV_CSR_WRITE(CSR_MHPMCOUNTER22, (value)); break;
        case 23: __RV_CSR_WRITE(CSR_MHPMCOUNTER23, (value)); break;
        case 24: __RV_CSR_WRITE(CSR_MHPMCOUNTER24, (value)); break;
        case 25: __RV_CSR_WRITE(CSR_MHPMCOUNTER25, (value)); break;
        case 26: __RV_CSR_WRITE(CSR_MHPMCOUNTER26, (value)); break;
        case 27: __RV_CSR_WRITE(CSR_MHPMCOUNTER27, (value)); break;
        case 28: __RV_CSR_WRITE(CSR_MHPMCOUNTER28, (value)); break;
        case 29: __RV_CSR_WRITE(CSR_MHPMCOUNTER29, (value)); break;
        case 30: __RV_CSR_WRITE(CSR_MHPMCOUNTER30, (value)); break;
        case 31: __RV_CSR_WRITE(CSR_MHPMCOUNTER31, (value)); break;
 
#else
#endif
        default: break;
    }
}

References __RV_CSR_WRITE, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11, CSR_MHPMCOUNTER11H, CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15, CSR_MHPMCOUNTER15H, CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19, CSR_MHPMCOUNTER19H, CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23, CSR_MHPMCOUNTER23H, CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27, CSR_MHPMCOUNTER27H, CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER3, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31, CSR_MHPMCOUNTER31H, CSR_MHPMCOUNTER3H, CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7, CSR_MHPMCOUNTER7H, CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9, and CSR_MHPMCOUNTER9H.

__set_hpm_event()

__STATIC_INLINE void __set_hpm_event	(	unsigned long	idx,
		unsigned long	event
	)

Set event for selected high performance monitor event.

Parameters

[in]	idx	HPMEVENTx CSR index(3-31)
[in]	event	HPMEVENTx Register value to set

Set event for high performance monitor event register

Definition at line 1711 of file core_feature_base.h.

{
    switch (idx) {
        case 3: __RV_CSR_WRITE(CSR_MHPMEVENT3, event); break;
        case 4: __RV_CSR_WRITE(CSR_MHPMEVENT4, event); break;
        case 5: __RV_CSR_WRITE(CSR_MHPMEVENT5, event); break;
        case 6: __RV_CSR_WRITE(CSR_MHPMEVENT6, event); break;
        case 7: __RV_CSR_WRITE(CSR_MHPMEVENT7, event); break;
        case 8: __RV_CSR_WRITE(CSR_MHPMEVENT8, event); break;
        case 9: __RV_CSR_WRITE(CSR_MHPMEVENT9, event); break;
        case 10: __RV_CSR_WRITE(CSR_MHPMEVENT10, event); break;
        case 11: __RV_CSR_WRITE(CSR_MHPMEVENT11, event); break;
        case 12: __RV_CSR_WRITE(CSR_MHPMEVENT12, event); break;
        case 13: __RV_CSR_WRITE(CSR_MHPMEVENT13, event); break;
        case 14: __RV_CSR_WRITE(CSR_MHPMEVENT14, event); break;
        case 15: __RV_CSR_WRITE(CSR_MHPMEVENT15, event); break;
        case 16: __RV_CSR_WRITE(CSR_MHPMEVENT16, event); break;
        case 17: __RV_CSR_WRITE(CSR_MHPMEVENT17, event); break;
        case 18: __RV_CSR_WRITE(CSR_MHPMEVENT18, event); break;
        case 19: __RV_CSR_WRITE(CSR_MHPMEVENT19, event); break;
        case 20: __RV_CSR_WRITE(CSR_MHPMEVENT20, event); break;
        case 21: __RV_CSR_WRITE(CSR_MHPMEVENT21, event); break;
        case 22: __RV_CSR_WRITE(CSR_MHPMEVENT22, event); break;
        case 23: __RV_CSR_WRITE(CSR_MHPMEVENT23, event); break;
        case 24: __RV_CSR_WRITE(CSR_MHPMEVENT24, event); break;
        case 25: __RV_CSR_WRITE(CSR_MHPMEVENT25, event); break;
        case 26: __RV_CSR_WRITE(CSR_MHPMEVENT26, event); break;
        case 27: __RV_CSR_WRITE(CSR_MHPMEVENT27, event); break;
        case 28: __RV_CSR_WRITE(CSR_MHPMEVENT28, event); break;
        case 29: __RV_CSR_WRITE(CSR_MHPMEVENT29, event); break;
        case 30: __RV_CSR_WRITE(CSR_MHPMEVENT30, event); break;
        case 31: __RV_CSR_WRITE(CSR_MHPMEVENT31, event); break;
        default: break;
    }
}

References __RV_CSR_WRITE, CSR_MHPMEVENT10, CSR_MHPMEVENT11, CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15, CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19, CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23, CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27, CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT3, CSR_MHPMEVENT30, CSR_MHPMEVENT31, CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7, CSR_MHPMEVENT8, and CSR_MHPMEVENT9.

__set_medeleg()

__STATIC_FORCEINLINE void __set_medeleg

(

unsigned long

mask

)

Set exceptions delegation to S mode.

Set certain exceptions of supervisor mode or user mode delegated from machined mode to supervisor mode.

Remarks

Exception should trigger in supervisor mode or user mode.

Definition at line 2184 of file core_feature_base.h.

{
    __RV_CSR_WRITE(CSR_MEDELEG, mask);
}

References __RV_CSR_WRITE, and CSR_MEDELEG.

__set_mideleg()

__STATIC_FORCEINLINE void __set_mideleg

(

unsigned long

mask

)

Set interrupt delegation to S mode.

Set certain interrupt of supervisor mode or user mode delegated from machined mode to supervisor mode.

Remarks

interrupt should trigger in supervisor mode or user mode.

Definition at line 2196 of file core_feature_base.h.

{
    __RV_CSR_WRITE(CSR_MIDELEG, mask);
}

References __RV_CSR_WRITE, and CSR_MIDELEG.

__set_wfi_sleepmode()

__STATIC_FORCEINLINE void __set_wfi_sleepmode

(

WFI_SleepMode_Type

mode

)

Set Sleep mode of WFI.

Set the SLEEPVALUE CSR register to control the WFI Sleep mode.

Parameters

[in]

mode

The sleep mode to be set

Definition at line 1580 of file core_feature_base.h.

{
    __RV_CSR_WRITE(CSR_SLEEPVALUE, mode);
}

References __RV_CSR_WRITE, and CSR_SLEEPVALUE.

__SH()

__STATIC_FORCEINLINE void __SH	(	volatile void *	addr,
		uint16_t	val
	)

Write 16bit value to address (16 bit)

Write 16 bit value.

Parameters

[in]	addr	Address pointer to data
[in]	val	Value to set

Definition at line 2277 of file core_feature_base.h.

{
    __ASM volatile ("sh %0, 0(%1)" : : "r" (val), "r" (addr));
}

References __ASM.

__SW()

__STATIC_FORCEINLINE void __SW	(	volatile void *	addr,
		uint32_t	val
	)

Write 32bit value to address (32 bit)

Write 32 bit value.

Parameters

[in]	addr	Address pointer to data
[in]	val	Value to set

Definition at line 2288 of file core_feature_base.h.

{
    __ASM volatile ("sw %0, 0(%1)" : : "r" (val), "r" (addr));
}

References __ASM.

Referenced by CIDU_AcquireSemaphore(), CIDU_BroadcastExtInterrupt(), CIDU_ClearInterCoreIntReq(), CIDU_ReleaseSemaphore(), CIDU_ResetFirstClaimMode(), CIDU_SetFirstClaimMode(), CIDU_TriggerInterCoreInt(), ECC_DLMErrInject(), ECC_DLMErrRestore(), ECC_ILMErrInject(), ECC_ILMErrRestore(), SMPCC_CLMErrInject(), SysTimer_ClearHartSWIRQ(), SysTimer_ClearHartSWIRQ_S(), SysTimer_ClearIPI(), SysTimer_ClearIPI_S(), SysTimer_SendIPI(), SysTimer_SendIPI_S(), SysTimer_SetHartCompareValue(), SysTimer_SetHartMsipValue(), SysTimer_SetHartSsipValue(), SysTimer_SetHartSWIRQ(), SysTimer_SetHartSWIRQ_S(), and SysTimer_SetLoadValue().

__TXEVT()

__STATIC_FORCEINLINE void __TXEVT

(

void

)

Send TX Event.

Set the CSR TXEVT to control send a TX Event. The Core will output signal tx_evt as output event signal.

Definition at line 1591 of file core_feature_base.h.

{
    __RV_CSR_SET(CSR_TXEVT, 0x1);
}

References __RV_CSR_SET, and CSR_TXEVT.

__WFE()

__STATIC_FORCEINLINE void __WFE

(

void

)

Wait For Event.

Wait For Event is executed using CSR_WFE.WFE=1 and WFI instruction. It will suspends execution until event, NMI or Debug happened. When Core is waked up, Core will resume previous execution

Definition at line 1535 of file core_feature_base.h.

{
    __RV_CSR_SET(CSR_WFE, WFE_WFE);
    __ASM volatile("wfi");
    __RV_CSR_CLEAR(CSR_WFE, WFE_WFE);
}

References __ASM, __RV_CSR_CLEAR, __RV_CSR_SET, CSR_WFE, and WFE_WFE.

__WFI()

__STATIC_FORCEINLINE void __WFI

(

void

)

Wait For Interrupt.

Wait For Interrupt is is executed using CSR_WFE.WFE=0 and WFI instruction. It will suspends execution until interrupt, NMI or Debug happened. When Core is waked up by interrupt, if

1. mstatus.MIE == 1(interrupt enabled), Core will enter ISR code
2. mstatus.MIE == 0(interrupt disabled), Core will resume previous execution

Definition at line 1522 of file core_feature_base.h.

{
    __RV_CSR_CLEAR(CSR_WFE, WFE_WFE);
    __ASM volatile("wfi");
}

References __ASM, __RV_CSR_CLEAR, CSR_WFE, and WFE_WFE.