NMSIS-Core  Version 1.6.0
NMSIS-Core support for Nuclei processor-based devices
core_feature_cache.h
1 /*
2  * Copyright (c) 2019 Nuclei Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Licensed under the Apache License, Version 2.0 (the License); you may
7  * not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  * www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  * See the License for the specific language governing permissions and
16  * limitations under the License.
17  */
18 #ifndef __CORE_FEATURE_CACHE_H__
19 #define __CORE_FEATURE_CACHE_H__
24 /*
25  * Cache Feature Configuration Macro:
26  * 1. __ICACHE_PRESENT: Define whether I-Cache Unit is present or not.
27  * * 0: Not present
28  * * 1: Present
29  * 2. __DCACHE_PRESENT: Define whether D-Cache Unit is present or not.
30  * * 0: Not present
31  * * 1: Present
32  * 3. __CCM_PRESENT: Define whether Nuclei Cache Control and Maintainence(CCM) Unit is present or not.
33  * * 0: Not present
34  * * 1: Present
35  * 4. __SMPCC_PRESENT: Define whether SMP & Cluster Cache Unit is present or not.
36  * * 0: Not present
37  * * 1: Present
38  * 5. __SMPCC_BASEADDR: Base address of the SMP & Cluster Cache unit.
39  */
40 #ifdef __cplusplus
41  extern "C" {
42 #endif
43 
44 #include "core_feature_base.h"
45 
46 
47 #if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1)
48 
49 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
62 typedef struct {
63  __IM uint8_t RESERVED0[16];
64  __IOM uint32_t CC_CTRL;
65  __IOM uint32_t CC_mCMD;
66  __IM uint8_t RESERVED1[168];
67  __IOM uint32_t CC_sCMD;
68  __IOM uint32_t CC_uCMD;
69  __IM uint8_t RESERVED2[20];
70  __IOM uint32_t CC_INVALID_ALL;
72 
73 #define SMPCC_CMD_CTRL_SUP_EN_Pos 9U
74 #define SMPCC_CMD_CTRL_SUP_EN_Msk (0x1UL << SMPCC_CMD_CTRL_SUP_EN_Pos)
75 #define SMPCC_CMD_CTRL_SUP_EN_ENABLE 1U
76 #define SMPCC_CMD_CTRL_SUP_EN_DISABLE 0U
78 #define SMPCC_CMD_CTRL_USE_EN_Pos 10U
79 #define SMPCC_CMD_CTRL_USE_EN_Msk (0x1UL << SMPCC_CMD_CTRL_USE_EN_Pos)
80 #define SMPCC_CMD_CTRL_USE_EN_ENABLE 1U
81 #define SMPCC_CMD_CTRL_USE_EN_DISABLE 0U
83 #define SMPCC_CMD_xCMD_CMD_Pos 0U
84 #define SMPCC_CMD_xCMD_CMD_Msk (0x1FUL << SMPCC_CMD_xCMD_CMD_Pos)
85 #define SMPCC_CMD_xCMD_CMD_WB_ALL 0x7U
86 #define SMPCC_CMD_xCMD_CMD_WBINVAL_ALL 0x6U
88 #define SMPCC_CMD_xCMD_STATUS_Pos 23U
89 #define SMPCC_CMD_xCMD_STATUS_Msk (0x7UL << SMPCC_CMD_xCMD_STATUS_Pos)
91 #define SMPCC_CMD_xCMD_RESULT_Pos 26U
92 #define SMPCC_CMD_xCMD_RESULT_Msk (0x1FUL << SMPCC_CMD_xCMD_RESULT_Pos)
93 #define SMPCC_CMD_xCMD_RESULT_SUCCESS 0x0U
94 #define SMPCC_CMD_xCMD_RESULT_ENTRY_EXCEED_LIMIT 0x1U
95 #define SMPCC_CMD_xCMD_RESULT_REFILL_BUS_ERROR 0x3U
96 #define SMPCC_CMD_xCMD_RESULT_ECC_ERROR 0x4U
97 #define SMPCC_CMD_xCMD_RESULT_CPBACK_BUS_ERROR 0x5U
99 #define SMPCC_CMD_xCMD_COMPLETE_Pos 31U
100 #define SMPCC_CMD_xCMD_COMPLETE_Msk (0x1UL << SMPCC_CMD_xCMD_COMPLETE_Pos)
102 #define SMPCC_CMD_INVALID_ALL_Pos 0U
103 #define SMPCC_CMD_INVALID_ALL_Msk (0x1UL << SMPCC_CMD_INVALID_ALL_Pos)
105 #ifndef __SMPCC_BASEADDR
106 /* Base address of SMPCC(__SMPCC_BASEADDR) should be defined in <Device.h> */
107 #error "__SMPCC_BASEADDR is not defined, please check!"
108 #endif
109 
110 /* SMPCC CMD registers Memory mapping of Device */
111 #define SMPCC_CMD_BASE __SMPCC_BASEADDR
112 #define SMPCC_CMD ((SMPCC_CMD_Type *)SMPCC_CMD_BASE) /* End of Doxygen Group NMSIS_Core_CCache */
115 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
116 
117 /* ########################## Cache functions #################################### */
142 typedef enum CCM_OP_FINFO {
147  CCM_OP_ECC_ERR = 0x4
149 
153 typedef enum CCM_CMD {
154  CCM_DC_INVAL = 0x0,
155  CCM_DC_WB = 0x1,
157  CCM_DC_LOCK = 0x3,
162  CCM_IC_INVAL = 0x8,
163  CCM_IC_LOCK = 0xb,
166  CCM_CC_LOCK = 0x13,
167  CCM_CC_UNLOCK = 0x12,
168 } CCM_CMD_Type;
169 
173 typedef struct CacheInfo {
174  uint32_t linesize;
175  uint32_t ways;
176  uint32_t setperway;
177  uint32_t size;
179 
180 #if __riscv_xlen == 32
181 #define CCM_SUEN_SUEN_Msk (0xFFFFFFFFUL)
182 #else
183 #define CCM_SUEN_SUEN_Msk (0xFFFFFFFFFFFFFFFFUL)
184 #endif
185 
199 {
201 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
202  SMPCC_CMD->CC_CTRL |= _VAL2FLD(SMPCC_CMD_CTRL_SUP_EN, SMPCC_CMD_CTRL_SUP_EN_ENABLE) |
203  _VAL2FLD(SMPCC_CMD_CTRL_USE_EN, SMPCC_CMD_CTRL_USE_EN_ENABLE);
204 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
205 }
206 
220 {
222 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
223  SMPCC_CMD->CC_CTRL &= ~(SMPCC_CMD_CTRL_SUP_EN_Msk | SMPCC_CMD_CTRL_USE_EN_Msk); /* Clear SUP_EN and USE_EN bits */
224 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
225 }
226 
237 {
239 } /* End of Doxygen Group NMSIS_Core_Cache */
241 
242 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
258 __STATIC_INLINE unsigned long MLockCCacheLine(unsigned long addr)
259 {
262  FlushPipeCCM();
263  __RWMB();
265 }
266 
279 __STATIC_INLINE unsigned long MLockCCacheLines(unsigned long addr, unsigned long cnt)
280 {
281  if (cnt > 0) {
282  unsigned long i;
283  unsigned long fail_info = CCM_OP_SUCCESS;
285  for (i = 0; i < cnt; i++) {
287  FlushPipeCCM();
288  __RWMB();
289  fail_info = __RV_CSR_READ(CSR_CCM_MDATA);
290  if (CCM_OP_SUCCESS != fail_info) {
291  return fail_info;
292  }
293  }
294  }
295  return CCM_OP_SUCCESS;
296 }
297 
308 __STATIC_INLINE unsigned long SLockCCacheLine(unsigned long addr)
309 {
312  FlushPipeCCM();
313  __RWMB();
315 }
316 
329 __STATIC_INLINE unsigned long SLockCCacheLines(unsigned long addr, unsigned long cnt)
330 {
331  if (cnt > 0) {
332  unsigned long i;
333  unsigned long fail_info = CCM_OP_SUCCESS;
335  for (i = 0; i < cnt; i++) {
337  FlushPipeCCM();
338  __RWMB();
339  fail_info = __RV_CSR_READ(CSR_CCM_SDATA);
340  if (CCM_OP_SUCCESS != fail_info) {
341  return fail_info;
342  }
343  }
344  }
345  return CCM_OP_SUCCESS;
346 }
347 
358 __STATIC_INLINE unsigned long ULockCCacheLine(unsigned long addr)
359 {
362  FlushPipeCCM();
363  __RWMB();
365 }
366 
379 __STATIC_INLINE unsigned long ULockCCacheLines(unsigned long addr, unsigned long cnt)
380 {
381  if (cnt > 0) {
382  unsigned long i;
383  unsigned long fail_info = CCM_OP_SUCCESS;
385  for (i = 0; i < cnt; i++) {
387  FlushPipeCCM();
388  __RWMB();
389  fail_info = __RV_CSR_READ(CSR_CCM_UDATA);
390  if (CCM_OP_SUCCESS != fail_info) {
391  return fail_info;
392  }
393  }
394  }
395  return CCM_OP_SUCCESS;
396 }
397 
407 __STATIC_INLINE void MUnlockCCacheLine(unsigned long addr)
408 {
411  FlushPipeCCM();
412  __RWMB();
413 }
414 
426 __STATIC_INLINE void MUnlockCCacheLines(unsigned long addr, unsigned long cnt)
427 {
428  if (cnt > 0) {
429  unsigned long i;
431  for (i = 0; i < cnt; i++) {
433  }
434  FlushPipeCCM();
435  __RWMB();
436  }
437 }
438 
448 __STATIC_INLINE void SUnlockCCacheLine(unsigned long addr)
449 {
452  FlushPipeCCM();
453  __RWMB();
454 }
455 
467 __STATIC_INLINE void SUnlockCCacheLines(unsigned long addr, unsigned long cnt)
468 {
469  if (cnt > 0) {
470  unsigned long i;
472  for (i = 0; i < cnt; i++) {
474  }
475  FlushPipeCCM();
476  __RWMB();
477  }
478 }
479 
489 __STATIC_INLINE void UUnlockCCacheLine(unsigned long addr)
490 {
493  FlushPipeCCM();
494  __RWMB();
495 }
496 
508 __STATIC_INLINE void UUnlockCCacheLines(unsigned long addr, unsigned long cnt)
509 {
510  if (cnt > 0) {
511  unsigned long i;
513  for (i = 0; i < cnt; i++) {
515  }
516  FlushPipeCCM();
517  __RWMB();
518  }
519 }
520  /* End of Doxygen Group NMSIS_Core_CCache */
522 #endif /* defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
523 
524 #endif /* defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) */
525 
526 #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)
527 
545 {
547  return 1;
548  }
549  return 0;
550 }
551 
563 {
565 }
566 
578 {
580 }
581 
593 {
595 }
596 
608 {
610 }
611 
612 #if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1)
624 {
625  if (info == NULL) {
626  return -1;
627  }
628  CSR_MICFGINFO_Type csr_ccfg;
629  csr_ccfg.d = __RV_CSR_READ(CSR_MICFG_INFO);
630  info->setperway = (1UL << csr_ccfg.b.set) << 3;
631  info->ways = (1 + csr_ccfg.b.way);
632  if (csr_ccfg.b.lsize == 0) {
633  info->linesize = 0;
634  } else {
635  info->linesize = (1UL << (csr_ccfg.b.lsize - 1)) << 3;
636  }
637  info->size = info->setperway * info->ways * info->linesize;
638  return 0;
639 }
640 
651 __STATIC_INLINE void MInvalICacheLine(unsigned long addr)
652 {
655  FlushPipeCCM();
656  __RWMB();
657 }
658 
670 __STATIC_INLINE void MInvalICacheLines(unsigned long addr, unsigned long cnt)
671 {
672  if (cnt > 0) {
673  unsigned long i;
675  for (i = 0; i < cnt; i++) {
677  }
678  FlushPipeCCM();
679  __RWMB();
680  }
681 }
682 
693 __STATIC_INLINE void SInvalICacheLine(unsigned long addr)
694 {
697  FlushPipeCCM();
698  __RWMB();
699 }
700 
712 __STATIC_INLINE void SInvalICacheLines(unsigned long addr, unsigned long cnt)
713 {
714  if (cnt > 0) {
715  unsigned long i;
717  for (i = 0; i < cnt; i++) {
719  }
720  FlushPipeCCM();
721  __RWMB();
722  }
723 }
724 
735 __STATIC_INLINE void UInvalICacheLine(unsigned long addr)
736 {
739  FlushPipeCCM();
740  __RWMB();
741 }
742 
754 __STATIC_INLINE void UInvalICacheLines(unsigned long addr, unsigned long cnt)
755 {
756  if (cnt > 0) {
757  unsigned long i;
759  for (i = 0; i < cnt; i++) {
761  }
762  FlushPipeCCM();
763  __RWMB();
764  }
765 }
766 
767 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
778 __STATIC_INLINE void MInvalICacheCCacheLine(unsigned long addr)
779 {
782  /* Trigger Cluster Cache invalidation by DC_INVAL */
784  FlushPipeCCM();
785  __RWMB();
786 }
787 
799 __STATIC_INLINE void MInvalICacheCCacheLines(unsigned long addr, unsigned long cnt)
800 {
801  if (cnt > 0) {
802  unsigned long i;
804  for (i = 0; i < cnt; i++) {
806  /* Trigger Cluster Cache invalidation by DC_INVAL */
808  }
809  FlushPipeCCM();
810  __RWMB();
811  }
812 }
813 
824 __STATIC_INLINE void SInvalICacheCCacheLine(unsigned long addr)
825 {
828  /* Trigger Cluster Cache invalidation by DC_INVAL */
830  FlushPipeCCM();
831  __RWMB();
832 }
833 
845 __STATIC_INLINE void SInvalICacheCCacheLines(unsigned long addr, unsigned long cnt)
846 {
847  if (cnt > 0) {
848  unsigned long i;
850  for (i = 0; i < cnt; i++) {
852  /* Trigger Cluster Cache invalidation by DC_INVAL */
854  }
855  FlushPipeCCM();
856  __RWMB();
857  }
858 }
859 
870 __STATIC_INLINE void UInvalICacheCCacheLine(unsigned long addr)
871 {
874  /* Trigger Cluster Cache invalidation by DC_INVAL */
876  FlushPipeCCM();
877  __RWMB();
878 }
879 
891 __STATIC_INLINE void UInvalICacheCCacheLines(unsigned long addr, unsigned long cnt)
892 {
893  if (cnt > 0) {
894  unsigned long i;
896  for (i = 0; i < cnt; i++) {
898  /* Trigger Cluster Cache invalidation by DC_INVAL */
900  }
901  FlushPipeCCM();
902  __RWMB();
903  }
904 }
905 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
906 
917 __STATIC_INLINE unsigned long MLockICacheLine(unsigned long addr)
918 {
921  FlushPipeCCM();
922  __RWMB();
924 }
925 
938 __STATIC_INLINE unsigned long MLockICacheLines(unsigned long addr, unsigned long cnt)
939 {
940  if (cnt > 0) {
941  unsigned long i;
942  unsigned long fail_info = CCM_OP_SUCCESS;
944  for (i = 0; i < cnt; i++) {
946  FlushPipeCCM();
947  __RWMB();
948  fail_info = __RV_CSR_READ(CSR_CCM_MDATA);
949  if (CCM_OP_SUCCESS != fail_info) {
950  return fail_info;
951  }
952  }
953  }
954  return CCM_OP_SUCCESS;
955 }
956 
967 __STATIC_INLINE unsigned long SLockICacheLine(unsigned long addr)
968 {
971  FlushPipeCCM();
972  __RWMB();
974 }
975 
988 __STATIC_INLINE unsigned long SLockICacheLines(unsigned long addr, unsigned long cnt)
989 {
990  if (cnt > 0) {
991  unsigned long i;
992  unsigned long fail_info = CCM_OP_SUCCESS;
994  for (i = 0; i < cnt; i++) {
996  FlushPipeCCM();
997  __RWMB();
998  fail_info = __RV_CSR_READ(CSR_CCM_SDATA);
999  if (CCM_OP_SUCCESS != fail_info) {
1000  return fail_info;
1001  }
1002  }
1003  }
1004  return CCM_OP_SUCCESS;
1005 }
1006 
1017 __STATIC_INLINE unsigned long ULockICacheLine(unsigned long addr)
1018 {
1021  FlushPipeCCM();
1022  __RWMB();
1023  return __RV_CSR_READ(CSR_CCM_UDATA);
1024 }
1025 
1038 __STATIC_INLINE unsigned long ULockICacheLines(unsigned long addr, unsigned long cnt)
1039 {
1040  if (cnt > 0) {
1041  unsigned long i;
1042  unsigned long fail_info = CCM_OP_SUCCESS;
1044  for (i = 0; i < cnt; i++) {
1046  FlushPipeCCM();
1047  __RWMB();
1048  fail_info = __RV_CSR_READ(CSR_CCM_UDATA);
1049  if (CCM_OP_SUCCESS != fail_info) {
1050  return fail_info;
1051  }
1052  }
1053  }
1054  return CCM_OP_SUCCESS;
1055 }
1056 
1066 __STATIC_INLINE void MUnlockICacheLine(unsigned long addr)
1067 {
1070  FlushPipeCCM();
1071  __RWMB();
1072 }
1073 
1085 __STATIC_INLINE void MUnlockICacheLines(unsigned long addr, unsigned long cnt)
1086 {
1087  if (cnt > 0) {
1088  unsigned long i;
1090  for (i = 0; i < cnt; i++) {
1092  }
1093  FlushPipeCCM();
1094  __RWMB();
1095  }
1096 }
1097 
1107 __STATIC_INLINE void SUnlockICacheLine(unsigned long addr)
1108 {
1111  FlushPipeCCM();
1112  __RWMB();
1113 }
1114 
1126 __STATIC_INLINE void SUnlockICacheLines(unsigned long addr, unsigned long cnt)
1127 {
1128  if (cnt > 0) {
1129  unsigned long i;
1131  for (i = 0; i < cnt; i++) {
1133  }
1134  FlushPipeCCM();
1135  __RWMB();
1136  }
1137 }
1138 
1148 __STATIC_INLINE void UUnlockICacheLine(unsigned long addr)
1149 {
1152  FlushPipeCCM();
1153  __RWMB();
1154 }
1155 
1167 __STATIC_INLINE void UUnlockICacheLines(unsigned long addr, unsigned long cnt)
1168 {
1169  if (cnt > 0) {
1170  unsigned long i;
1172  for (i = 0; i < cnt; i++) {
1174  }
1175  FlushPipeCCM();
1176  __RWMB();
1177  }
1178 }
1179 
1190 {
1192  FlushPipeCCM();
1193  __RWMB();
1194 }
1195 
1206 {
1208  FlushPipeCCM();
1209  __RWMB();
1210 }
1211 
1222 {
1224  FlushPipeCCM();
1225  __RWMB();
1226 }
1227 
1228 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
1237 {
1238  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
1239  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
1240  __RWMB();
1241 }
1242 
1251 {
1252  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
1253  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
1254  __RWMB();
1255 }
1256 
1265 {
1266  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
1267  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
1268  __RWMB();
1269 }
1270 
1280 {
1282  FlushPipeCCM();
1283  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
1284  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
1285  __RWMB();
1286 }
1287 
1297 {
1299  FlushPipeCCM();
1300  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
1301  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
1302  __RWMB();
1303 }
1304 
1314 {
1316  FlushPipeCCM();
1317  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
1318  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
1319  __RWMB();
1320 }
1321 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
1322 
1323 #endif /* defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) */ /* End of Doxygen Group NMSIS_Core_ICache */
1325 #endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */
1326 
1327 #if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)
1345 {
1347  return 1;
1348  }
1349  return 0;
1350 }
1351 
1363 {
1365 }
1366 
1378 {
1380 }
1381 
1393 {
1395 }
1396 
1408 {
1410 }
1411 
1412 #if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1)
1424 {
1425  if (info == NULL) {
1426  return -1;
1427  }
1428  CSR_MDCFGINFO_Type csr_ccfg;
1429  csr_ccfg.d = __RV_CSR_READ(CSR_MDCFG_INFO);
1430  info->setperway = (1UL << csr_ccfg.b.set) << 3;
1431  info->ways = (1 + csr_ccfg.b.way);
1432  if (csr_ccfg.b.lsize == 0) {
1433  info->linesize = 0;
1434  } else {
1435  info->linesize = (1UL << (csr_ccfg.b.lsize - 1)) << 3;
1436  }
1437  info->size = info->setperway * info->ways * info->linesize;
1438  return 0;
1439 }
1440 
1451 __STATIC_INLINE void MInvalDCacheLine(unsigned long addr)
1452 {
1455  FlushPipeCCM();
1456  __RWMB();
1457 }
1458 
1470 __STATIC_INLINE void MInvalDCacheLines(unsigned long addr, unsigned long cnt)
1471 {
1472  if (cnt > 0) {
1473  unsigned long i;
1475  for (i = 0; i < cnt; i++) {
1477  }
1478  FlushPipeCCM();
1479  __RWMB();
1480  }
1481 }
1482 
1493 __STATIC_INLINE void SInvalDCacheLine(unsigned long addr)
1494 {
1497  FlushPipeCCM();
1498  __RWMB();
1499 }
1500 
1512 __STATIC_INLINE void SInvalDCacheLines(unsigned long addr, unsigned long cnt)
1513 {
1514  if (cnt > 0) {
1515  unsigned long i;
1517  for (i = 0; i < cnt; i++) {
1519  }
1520  FlushPipeCCM();
1521  __RWMB();
1522  }
1523 }
1524 
1535 __STATIC_INLINE void UInvalDCacheLine(unsigned long addr)
1536 {
1539  FlushPipeCCM();
1540  __RWMB();
1541 }
1542 
1554 __STATIC_INLINE void UInvalDCacheLines(unsigned long addr, unsigned long cnt)
1555 {
1556  if (cnt > 0) {
1557  unsigned long i;
1559  for (i = 0; i < cnt; i++) {
1561  }
1562  FlushPipeCCM();
1563  __RWMB();
1564  }
1565 }
1566 
1576 __STATIC_INLINE void MFlushDCacheLine(unsigned long addr)
1577 {
1580  FlushPipeCCM();
1581  __RWMB();
1582 }
1583 
1595 __STATIC_INLINE void MFlushDCacheLines(unsigned long addr, unsigned long cnt)
1596 {
1597  if (cnt > 0) {
1598  unsigned long i;
1600  for (i = 0; i < cnt; i++) {
1602  }
1603  FlushPipeCCM();
1604  __RWMB();
1605  }
1606 }
1607 
1617 __STATIC_INLINE void SFlushDCacheLine(unsigned long addr)
1618 {
1621  FlushPipeCCM();
1622  __RWMB();
1623 }
1624 
1636 __STATIC_INLINE void SFlushDCacheLines(unsigned long addr, unsigned long cnt)
1637 {
1638  if (cnt > 0) {
1639  unsigned long i;
1641  for (i = 0; i < cnt; i++) {
1643  }
1644  FlushPipeCCM();
1645  __RWMB();
1646  }
1647 }
1648 
1658 __STATIC_INLINE void UFlushDCacheLine(unsigned long addr)
1659 {
1662  FlushPipeCCM();
1663  __RWMB();
1664 }
1665 
1677 __STATIC_INLINE void UFlushDCacheLines(unsigned long addr, unsigned long cnt)
1678 {
1679  if (cnt > 0) {
1680  unsigned long i;
1682  for (i = 0; i < cnt; i++) {
1684  }
1685  FlushPipeCCM();
1686  __RWMB();
1687  }
1688 }
1689 
1699 __STATIC_INLINE void MFlushInvalDCacheLine(unsigned long addr)
1700 {
1703  FlushPipeCCM();
1704  __RWMB();
1705 }
1706 
1718 __STATIC_INLINE void MFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
1719 {
1720  if (cnt > 0) {
1721  unsigned long i;
1723  for (i = 0; i < cnt; i++) {
1725  }
1726  FlushPipeCCM();
1727  __RWMB();
1728  }
1729 }
1730 
1740 __STATIC_INLINE void SFlushInvalDCacheLine(unsigned long addr)
1741 {
1744  FlushPipeCCM();
1745  __RWMB();
1746 }
1747 
1759 __STATIC_INLINE void SFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
1760 {
1761  if (cnt > 0) {
1762  unsigned long i;
1764  for (i = 0; i < cnt; i++) {
1766  }
1767  FlushPipeCCM();
1768  __RWMB();
1769  }
1770 }
1771 
1781 __STATIC_INLINE void UFlushInvalDCacheLine(unsigned long addr)
1782 {
1785  FlushPipeCCM();
1786  __RWMB();
1787 }
1788 
1800 __STATIC_INLINE void UFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
1801 {
1802  if (cnt > 0) {
1803  unsigned long i;
1805  for (i = 0; i < cnt; i++) {
1807  }
1808  FlushPipeCCM();
1809  __RWMB();
1810  }
1811 }
1812 
1813 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
1822 #define MInvalDCacheCCacheLine(addr) MInvalDCacheLine(addr)
1823 
1833 #define MInvalDCacheCCacheLines(addr, cnt) MInvalDCacheLines(addr, cnt)
1834 
1843 #define SInvalDCacheCCacheLine(addr) SInvalDCacheLine(addr)
1844 
1854 #define SInvalDCacheCCacheLines(addr, cnt) SInvalDCacheLines(addr, cnt)
1855 
1864 #define UInvalDCacheCCacheLine(addr) UInvalDCacheLine(addr)
1865 
1875 #define UInvalDCacheCCacheLines(addr, cnt) UInvalDCacheLines(addr, cnt)
1884 #define MFlushDCacheCCacheLine(addr) MFlushDCacheLine(addr)
1885 
1895 #define MFlushDCacheCCacheLines(addr, cnt) MFlushDCacheLines(addr, cnt)
1896 
1905 #define SFlushDCacheCCacheLine(addr) SFlushDCacheLine(addr)
1906 
1916 #define SFlushDCacheCCacheLines(addr, cnt) SFlushDCacheLines(addr, cnt)
1917 
1926 #define UFlushDCacheCCacheLine(addr) UFlushDCacheLine(addr)
1927 
1937 #define UFlushDCacheCCacheLines(addr, cnt) UFlushDCacheLines(addr, cnt)
1946 #define MFlushInvalDCacheCCacheLine(addr) MFlushInvalDCacheLine(addr)
1947 
1957 #define MFlushInvalDCacheCCacheLines(addr, cnt) MFlushInvalDCacheLines(addr, cnt)
1958 
1967 #define SFlushInvalDCacheCCacheLine(addr) SFlushInvalDCacheLine(addr)
1968 
1978 #define SFlushInvalDCacheCCacheLines(addr, cnt) SFlushInvalDCacheLines(addr, cnt)
1979 
1988 #define UFlushInvalDCacheCCacheLine(addr) UFlushInvalDCacheLine(addr)
1989 
1999 #define UFlushInvalDCacheCCacheLines(addr, cnt) UFlushInvalDCacheLines(addr, cnt)
2000 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
2001 
2012 __STATIC_INLINE unsigned long MLockDCacheLine(unsigned long addr)
2013 {
2016  FlushPipeCCM();
2017  __RWMB();
2018  return __RV_CSR_READ(CSR_CCM_MDATA);
2019 }
2020 
2033 __STATIC_INLINE unsigned long MLockDCacheLines(unsigned long addr, unsigned long cnt)
2034 {
2035  if (cnt > 0) {
2036  unsigned long i;
2037  unsigned long fail_info = CCM_OP_SUCCESS;
2039  for (i = 0; i < cnt; i++) {
2041  FlushPipeCCM();
2042  __RWMB();
2043  fail_info = __RV_CSR_READ(CSR_CCM_MDATA);
2044  if (CCM_OP_SUCCESS != fail_info) {
2045  return fail_info;
2046  }
2047  }
2048  }
2049  return CCM_OP_SUCCESS;
2050 }
2051 
2062 __STATIC_INLINE unsigned long SLockDCacheLine(unsigned long addr)
2063 {
2066  FlushPipeCCM();
2067  __RWMB();
2068  return __RV_CSR_READ(CSR_CCM_SDATA);
2069 }
2070 
2083 __STATIC_INLINE unsigned long SLockDCacheLines(unsigned long addr, unsigned long cnt)
2084 {
2085  if (cnt > 0) {
2086  unsigned long i;
2087  unsigned long fail_info = CCM_OP_SUCCESS;
2089  for (i = 0; i < cnt; i++) {
2091  FlushPipeCCM();
2092  __RWMB();
2093  fail_info = __RV_CSR_READ(CSR_CCM_SDATA);
2094  if (CCM_OP_SUCCESS != fail_info) {
2095  return fail_info;
2096  }
2097  }
2098  }
2099  return CCM_OP_SUCCESS;
2100 }
2101 
2112 __STATIC_INLINE unsigned long ULockDCacheLine(unsigned long addr)
2113 {
2116  FlushPipeCCM();
2117  __RWMB();
2118  return __RV_CSR_READ(CSR_CCM_UDATA);
2119 }
2120 
2133 __STATIC_INLINE unsigned long ULockDCacheLines(unsigned long addr, unsigned long cnt)
2134 {
2135  if (cnt > 0) {
2136  unsigned long i;
2137  unsigned long fail_info = CCM_OP_SUCCESS;
2139  for (i = 0; i < cnt; i++) {
2141  FlushPipeCCM();
2142  __RWMB();
2143  fail_info = __RV_CSR_READ(CSR_CCM_UDATA);
2144  if (CCM_OP_SUCCESS != fail_info) {
2145  return fail_info;
2146  }
2147  }
2148  }
2149  return CCM_OP_SUCCESS;
2150 }
2151 
2161 __STATIC_INLINE void MUnlockDCacheLine(unsigned long addr)
2162 {
2165  FlushPipeCCM();
2166  __RWMB();
2167 }
2168 
2180 __STATIC_INLINE void MUnlockDCacheLines(unsigned long addr, unsigned long cnt)
2181 {
2182  if (cnt > 0) {
2183  unsigned long i;
2185  for (i = 0; i < cnt; i++) {
2187  }
2188  FlushPipeCCM();
2189  __RWMB();
2190  }
2191 }
2192 
2202 __STATIC_INLINE void SUnlockDCacheLine(unsigned long addr)
2203 {
2206  FlushPipeCCM();
2207  __RWMB();
2208 }
2209 
2221 __STATIC_INLINE void SUnlockDCacheLines(unsigned long addr, unsigned long cnt)
2222 {
2223  if (cnt > 0) {
2224  unsigned long i;
2226  for (i = 0; i < cnt; i++) {
2228  }
2229  FlushPipeCCM();
2230  __RWMB();
2231  }
2232 }
2233 
2243 __STATIC_INLINE void UUnlockDCacheLine(unsigned long addr)
2244 {
2247  FlushPipeCCM();
2248  __RWMB();
2249 }
2250 
2262 __STATIC_INLINE void UUnlockDCacheLines(unsigned long addr, unsigned long cnt)
2263 {
2264  if (cnt > 0) {
2265  unsigned long i;
2267  for (i = 0; i < cnt; i++) {
2269  }
2270  FlushPipeCCM();
2271  __RWMB();
2272  }
2273 }
2274 
2285 {
2287  FlushPipeCCM();
2288  __RWMB();
2289 }
2290 
2301 {
2303  FlushPipeCCM();
2304  __RWMB();
2305 }
2306 
2319 {
2321  FlushPipeCCM();
2322  __RWMB();
2323 }
2324 
2335 {
2337  FlushPipeCCM();
2338  __RWMB();
2339 }
2340 
2351 {
2353  FlushPipeCCM();
2354  __RWMB();
2355 }
2356 
2367 {
2369  FlushPipeCCM();
2370  __RWMB();
2371 }
2372 
2383 {
2385  FlushPipeCCM();
2386  __RWMB();
2387 }
2388 
2399 {
2401  FlushPipeCCM();
2402  __RWMB();
2403 }
2404 
2415 {
2417  FlushPipeCCM();
2418  __RWMB();
2419 }
2420 
2421 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
2432 {
2433  /* Clear pending error status before issuing the Cluster Cache command.
2434  * RESC/FESC/BESC are write-1-to-clear bits, so read the status and write it back. */
2435  SMPCC_CMD->CC_mCMD = (SMPCC_CMD->CC_mCMD & SMPCC_CMD_xCMD_STATUS_Msk);
2436  SMPCC_CMD->CC_mCMD = (SMPCC_CMD->CC_mCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2437  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WB_ALL);
2438  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_mCMD) == 0);
2439  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_mCMD);
2440  __RWMB();
2441  return res;
2442 }
2443 
2454 {
2455  /* Clear pending error status before issuing the Cluster Cache command.
2456  * RESC/FESC/BESC are write-1-to-clear bits, so read the status and write it back. */
2457  SMPCC_CMD->CC_sCMD = (SMPCC_CMD->CC_sCMD & SMPCC_CMD_xCMD_STATUS_Msk);
2458  SMPCC_CMD->CC_sCMD = (SMPCC_CMD->CC_sCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2459  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WB_ALL);
2460  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_sCMD) == 0);
2461  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_sCMD);
2462  __RWMB();
2463  return res;
2464 }
2465 
2476 {
2477  /* Clear pending error status before issuing the Cluster Cache command.
2478  * RESC/FESC/BESC are write-1-to-clear bits, so read the status and write it back. */
2479  SMPCC_CMD->CC_uCMD = (SMPCC_CMD->CC_uCMD & SMPCC_CMD_xCMD_STATUS_Msk);
2480  SMPCC_CMD->CC_uCMD = (SMPCC_CMD->CC_uCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2481  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WB_ALL);
2482  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_uCMD) == 0);
2483  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_uCMD);
2484  __RWMB();
2485  return res;
2486 }
2487 
2498 {
2499  SMPCC_CMD->CC_mCMD = (SMPCC_CMD->CC_mCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2500  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WBINVAL_ALL);
2501  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_mCMD) == 0);
2502  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_mCMD);
2503  __RWMB();
2504  return res;
2505 }
2506 
2517 {
2518  SMPCC_CMD->CC_sCMD = (SMPCC_CMD->CC_sCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2519  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WBINVAL_ALL);
2520  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_sCMD) == 0);
2521  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_sCMD);
2522  __RWMB();
2523  return res;
2524 }
2525 
2536 {
2537  SMPCC_CMD->CC_uCMD = (SMPCC_CMD->CC_uCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2538  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WBINVAL_ALL);
2539  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_uCMD) == 0);
2540  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_uCMD);
2541  __RWMB();
2542  return res;
2543 }
2544 
2554 {
2556  FlushPipeCCM();
2557  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
2558  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
2559  __RWMB();
2560 }
2561 
2571 {
2573  FlushPipeCCM();
2574  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
2575  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
2576  __RWMB();
2577 }
2578 
2588 {
2590  FlushPipeCCM();
2591  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
2592  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
2593  __RWMB();
2594 }
2595 
2606 {
2608  FlushPipeCCM();
2609  SMPCC_CMD->CC_mCMD = (SMPCC_CMD->CC_mCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2610  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WB_ALL);
2611  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_mCMD) == 0);
2612  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_mCMD);
2613  __RWMB();
2614  return res;
2615 }
2616 
2627 {
2629  FlushPipeCCM();
2630  SMPCC_CMD->CC_sCMD = (SMPCC_CMD->CC_sCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2631  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WB_ALL);
2632  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_sCMD) == 0);
2633  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_sCMD);
2634  __RWMB();
2635  return res;
2636 }
2637 
2648 {
2650  FlushPipeCCM();
2651  SMPCC_CMD->CC_uCMD = (SMPCC_CMD->CC_uCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2652  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WB_ALL);
2653  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_uCMD) == 0);
2654  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_uCMD);
2655  __RWMB();
2656  return res;
2657 }
2658 
2669 {
2671  FlushPipeCCM();
2672  SMPCC_CMD->CC_mCMD = (SMPCC_CMD->CC_mCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2673  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WBINVAL_ALL);
2674  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_mCMD) == 0);
2675  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_mCMD);
2676  __RWMB();
2677  return res;
2678 }
2679 
2690 {
2692  FlushPipeCCM();
2693  SMPCC_CMD->CC_sCMD = (SMPCC_CMD->CC_sCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2694  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WBINVAL_ALL);
2695  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_sCMD) == 0);
2696  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_sCMD);
2697  __RWMB();
2698  return res;
2699 }
2700 
2711 {
2713  FlushPipeCCM();
2714  SMPCC_CMD->CC_uCMD = (SMPCC_CMD->CC_uCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2715  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WBINVAL_ALL);
2716  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_uCMD) == 0);
2717  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_uCMD);
2718  __RWMB();
2719  return res;
2720 }
2721 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
2722 
2723 #endif /* defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) */
2724  /* End of Doxygen Group NMSIS_Core_DCache */
2726 #endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */
2727 
2728 #ifdef __cplusplus
2729 }
2730 #endif
2731 #endif /* __CORE_FEATURE_CACHE_H__ */
__STATIC_INLINE void UUnlockCCacheLine(unsigned long addr)
Unlock one Cluster Cache line specified by address in U-Mode.
__STATIC_INLINE void SUnlockCCacheLine(unsigned long addr)
Unlock one Cluster Cache line specified by address in S-Mode.
#define SMPCC_CMD_CTRL_USE_EN_ENABLE
SMPCC_CMD CC_CTRL USE_EN Enable.
__STATIC_INLINE unsigned long MLockCCacheLine(unsigned long addr)
Lock one Cluster Cache line specified by address in M-Mode.
#define SMPCC_CMD
SMPCC CMD configuration struct.
__STATIC_INLINE unsigned long SLockCCacheLine(unsigned long addr)
Lock one Cluster Cache line specified by address in S-Mode.
__STATIC_INLINE void UUnlockCCacheLines(unsigned long addr, unsigned long cnt)
Unlock several Cluster Cache lines specified by address in U-Mode.
#define SMPCC_CMD_xCMD_CMD_WB_ALL
SMPCC_CMD xCMD CMD WB_ALL.
__STATIC_INLINE unsigned long MLockCCacheLines(unsigned long addr, unsigned long cnt)
Lock several Cluster Cache lines specified by address in M-Mode.
__STATIC_INLINE unsigned long ULockCCacheLine(unsigned long addr)
Lock one Cluster Cache line specified by address in U-Mode.
__STATIC_INLINE void SUnlockCCacheLines(unsigned long addr, unsigned long cnt)
Unlock several Cluster Cache lines specified by address in S-Mode.
#define SMPCC_CMD_xCMD_STATUS_Msk
SMPCC_CMD register xCMD field RESC/FESC/BESC Mask.
__STATIC_INLINE void MUnlockCCacheLines(unsigned long addr, unsigned long cnt)
Unlock several Cluster Cache lines specified by address in M-Mode.
#define SMPCC_CMD_xCMD_CMD_WBINVAL_ALL
SMPCC_CMD xCMD CMD WBINVAL_ALL.
#define SMPCC_CMD_xCMD_CMD_Msk
SMPCC_CMD register xCMD field CMD Mask.
__STATIC_INLINE unsigned long ULockCCacheLines(unsigned long addr, unsigned long cnt)
Lock several Cluster Cache lines specified by address in U-Mode.
__STATIC_INLINE unsigned long SLockCCacheLines(unsigned long addr, unsigned long cnt)
Lock several Cluster Cache lines specified by address in S-Mode.
#define SMPCC_CMD_CTRL_USE_EN_Msk
SMPCC_CMD CC_CTRL USE_EN Mask.
#define SMPCC_CMD_CTRL_SUP_EN_Msk
SMPCC_CMD CC_CTRL SUP_EN Mask.
#define SMPCC_CMD_CTRL_SUP_EN_ENABLE
SMPCC_CMD CC_CTRL SUP_EN Enable.
__STATIC_INLINE void MUnlockCCacheLine(unsigned long addr)
Unlock one Cluster Cache line specified by address in M-Mode.
#define MCACHE_CTL_IC_EN
#define MCACHE_CTL_DC_ECC_EN
#define MCFG_INFO_DCACHE
#define MCACHE_CTL_IC_ECC_EN
#define MCFG_INFO_ICACHE
#define MCACHE_CTL_DC_EN
#define __RV_CSR_CLEAR(csr, val)
CSR operation Macro for csrc instruction.
#define __RV_CSR_READ(csr)
CSR operation Macro for csrr instruction.
#define __RWMB()
Read & Write Memory barrier.
#define __RV_CSR_WRITE(csr, val)
CSR operation Macro for csrw instruction.
#define __RV_CSR_SET(csr, val)
CSR operation Macro for csrs instruction.
#define CSR_CCM_MCOMMAND
#define CSR_CCM_SCOMMAND
#define CSR_MICFG_INFO
#define CSR_CCM_MBEGINADDR
#define CSR_CCM_UCOMMAND
#define CSR_CCM_SDATA
#define CSR_CCM_SUEN
#define CSR_CCM_MDATA
#define CSR_MCACHE_CTL
#define CSR_CCM_FPIPE
#define CSR_MCFG_INFO
#define CSR_CCM_SBEGINADDR
#define CSR_CCM_UBEGINADDR
#define CSR_MDCFG_INFO
#define CSR_CCM_UDATA
CCM_OP_FINFO_Type
Cache CCM Operation Fail Info.
__STATIC_FORCEINLINE void FlushPipeCCM(void)
Flush pipeline after CCM operation.
CCM_CMD_Type
Cache CCM Command Types.
__STATIC_FORCEINLINE void DisableSUCCM(void)
Disable CCM operation in Supervisor/User Mode.
#define CCM_SUEN_SUEN_Msk
CSR CCM_SUEN: SUEN Mask.
__STATIC_FORCEINLINE void EnableSUCCM(void)
Enable CCM operation in Supervisor/User Mode.
@ CCM_OP_REFILL_BUS_ERR
Refill has Bus Error.
@ CCM_OP_ECC_ERR
Deprecated, ECC Error, this error code is removed in later Nuclei CCM RTL design, please don't use it...
@ CCM_OP_PERM_CHECK_ERR
PMP/sPMP/Page-Table X(I-Cache)/R(D-Cache) permission check failed, or belong to Device/Non-Cacheable ...
@ CCM_OP_SUCCESS
Lock Succeed.
@ CCM_OP_EXCEED_ERR
Exceed the the number of lockable ways(N-Way I/D-Cache, lockable is N-1)
@ CCM_DC_WB
Flush the specific D-Cache line and Cluster Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_DC_INVAL
Unlock and invalidate D-Cache line and Cluster Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_DC_WBINVAL
Unlock, flush and invalidate the specific D-Cache line and Cluster Cache line specified by CSR CCM_XB...
@ CCM_DC_LOCK
Lock the specific D-Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_IC_INVAL
Unlock and invalidate I-Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_IC_LOCK
Lock the specific I-Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_DC_WB_ALL
Flush all the valid and dirty D-Cache lines.
@ CCM_DC_INVAL_ALL
Unlock and invalidate all the D-Cache lines.
@ CCM_IC_INVAL_ALL
Unlock and invalidate all the I-Cache lines.
@ CCM_CC_LOCK
Lock the specific Cluster Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_DC_WBINVAL_ALL
Unlock and flush and invalidate all the valid and dirty D-Cache lines.
@ CCM_DC_UNLOCK
Unlock the specific D-Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_CC_UNLOCK
Unlock the specific Cluster Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_IC_UNLOCK
Unlock the specific I-Cache line specified by CSR CCM_XBEGINADDR.
#define __STATIC_FORCEINLINE
Define a static function that should be always inlined by the compiler.
Definition: nmsis_gcc.h:70
#define __STATIC_INLINE
Define a static function that may be inlined by the compiler.
Definition: nmsis_gcc.h:65
__STATIC_INLINE void MFlushDCache(void)
Flush all D-Cache lines in M-Mode.
__STATIC_INLINE unsigned long SLockDCacheLine(unsigned long addr)
Lock one D-Cache line specified by address in S-Mode.
__STATIC_INLINE void MInvalDCacheLines(unsigned long addr, unsigned long cnt)
Invalidate several D-Cache lines specified by address in M-Mode.
__STATIC_INLINE void UInvalDCacheLine(unsigned long addr)
Invalidate one D-Cache line specified by address in U-Mode.
__STATIC_INLINE void UUnlockDCacheLine(unsigned long addr)
Unlock one D-Cache line specified by address in U-Mode.
__STATIC_INLINE void UInvalDCache(void)
Invalidate all D-Cache lines in U-Mode.
__STATIC_INLINE void UFlushDCacheLines(unsigned long addr, unsigned long cnt)
Flush several D-Cache lines specified by address in U-Mode.
__STATIC_INLINE int32_t SFlushDCacheCCache(void)
Flush all D-Cache and Cluster Cache in S-Mode.
__STATIC_INLINE void SInvalDCacheCCache(void)
Invalidate all D-Cache and Cluster Cache in S-Mode.
__STATIC_INLINE void MFlushDCacheLines(unsigned long addr, unsigned long cnt)
Flush several D-Cache lines specified by address in M-Mode.
__STATIC_INLINE unsigned long ULockDCacheLines(unsigned long addr, unsigned long cnt)
Lock several D-Cache lines specified by address in U-Mode.
__STATIC_INLINE int32_t UFlushDCacheCCache(void)
Flush all D-Cache and Cluster Cache in U-Mode.
__STATIC_INLINE void MInvalDCacheLine(unsigned long addr)
Invalidate one D-Cache line specified by address in M-Mode.
__STATIC_INLINE void SInvalDCacheLines(unsigned long addr, unsigned long cnt)
Invalidate several D-Cache lines specified by address in S-Mode.
__STATIC_INLINE int32_t GetDCacheInfo(CacheInfo_Type *info)
Get D-Cache Information.
__STATIC_INLINE int32_t SFlushInvalCCache(void)
Flush and invalidate all Cluster Cache in S-Mode.
__STATIC_INLINE void SUnlockDCacheLine(unsigned long addr)
Unlock one D-Cache line specified by address in S-Mode.
__STATIC_INLINE void UFlushDCache(void)
Flush all D-Cache lines in U-Mode.
__STATIC_INLINE void MUnlockDCacheLine(unsigned long addr)
Unlock one D-Cache line specified by address in M-Mode.
__STATIC_INLINE void MFlushInvalDCache(void)
Flush and invalidate all D-Cache lines in M-Mode.
__STATIC_INLINE void UFlushDCacheLine(unsigned long addr)
Flush one D-Cache line specified by address in U-Mode.
__STATIC_FORCEINLINE void EnableDCacheECC(void)
Enable DCache ECC.
__STATIC_INLINE void SUnlockDCacheLines(unsigned long addr, unsigned long cnt)
Unlock several D-Cache lines specified by address in S-Mode.
__STATIC_INLINE void MFlushInvalDCacheLine(unsigned long addr)
Flush and invalidate one D-Cache line specified by address in M-Mode.
__STATIC_INLINE void UFlushInvalDCacheLine(unsigned long addr)
Flush and invalidate one D-Cache line specified by address in U-Mode.
__STATIC_INLINE int32_t UFlushInvalDCacheCCache(void)
Flush and invalidate all D-Cache and Cluster Cache in U-Mode.
__STATIC_INLINE unsigned long ULockDCacheLine(unsigned long addr)
Lock one D-Cache line specified by address in U-Mode.
__STATIC_INLINE void SFlushInvalDCacheLine(unsigned long addr)
Flush and invalidate one D-Cache line specified by address in S-Mode.
__STATIC_INLINE void SFlushDCache(void)
Flush all D-Cache lines in S-Mode.
__STATIC_INLINE int32_t DCachePresent(void)
Check DCache Unit Present or Not.
__STATIC_INLINE void MUnlockDCacheLines(unsigned long addr, unsigned long cnt)
Unlock several D-Cache lines specified by address in M-Mode.
__STATIC_INLINE int32_t UFlushCCache(void)
Flush all Cluster Cache in U-Mode.
__STATIC_INLINE void SFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
Flush and invalidate several D-Cache lines specified by address in S-Mode.
__STATIC_INLINE void UUnlockDCacheLines(unsigned long addr, unsigned long cnt)
Unlock several D-Cache lines specified by address in U-Mode.
__STATIC_INLINE void MInvalDCacheCCache(void)
Invalidate all D-Cache and Cluster Cache in M-Mode.
__STATIC_INLINE int32_t SFlushInvalDCacheCCache(void)
Flush and invalidate all D-Cache and Cluster Cache in S-Mode.
__STATIC_INLINE void SFlushDCacheLines(unsigned long addr, unsigned long cnt)
Flush several D-Cache lines specified by address in S-Mode.
__STATIC_FORCEINLINE void DisableDCache(void)
Disable DCache.
__STATIC_INLINE unsigned long MLockDCacheLine(unsigned long addr)
Lock one D-Cache line specified by address in M-Mode.
__STATIC_INLINE void UInvalDCacheCCache(void)
Invalidate all D-Cache and Cluster Cache in U-Mode.
__STATIC_INLINE void MFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
Flush and invalidate several D-Cache lines specified by address in M-Mode.
__STATIC_INLINE void SInvalDCacheLine(unsigned long addr)
Invalidate one D-Cache line specified by address in S-Mode.
__STATIC_INLINE void UInvalDCacheLines(unsigned long addr, unsigned long cnt)
Invalidate several D-Cache lines specified by address in U-Mode.
__STATIC_INLINE void UFlushInvalDCache(void)
Flush and invalidate all D-Cache lines in U-Mode.
__STATIC_FORCEINLINE void DisableDCacheECC(void)
Disable DCache ECC.
__STATIC_INLINE unsigned long MLockDCacheLines(unsigned long addr, unsigned long cnt)
Lock several D-Cache lines specified by address in M-Mode.
__STATIC_INLINE int32_t UFlushInvalCCache(void)
Flush and invalidate all Cluster Cache in U-Mode.
__STATIC_INLINE void MFlushDCacheLine(unsigned long addr)
Flush one D-Cache line specified by address in M-Mode.
__STATIC_INLINE void SInvalDCache(void)
Invalidate all D-Cache lines in S-Mode.
__STATIC_INLINE int32_t SFlushCCache(void)
Flush all Cluster Cache in S-Mode.
__STATIC_INLINE int32_t MFlushDCacheCCache(void)
Flush all D-Cache and Cluster Cache in M-Mode.
__STATIC_INLINE void MInvalDCache(void)
Invalidate all D-Cache lines in M-Mode.
__STATIC_INLINE int32_t MFlushInvalCCache(void)
Flush and invalidate all Cluster Cache in M-Mode.
__STATIC_INLINE int32_t MFlushInvalDCacheCCache(void)
Flush and invalidate all D-Cache and Cluster Cache in M-Mode.
__STATIC_INLINE void SFlushInvalDCache(void)
Flush and invalidate all D-Cache lines in S-Mode.
__STATIC_INLINE void UFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
Flush and invalidate several D-Cache lines specified by address in U-Mode.
__STATIC_FORCEINLINE void EnableDCache(void)
Enable DCache.
__STATIC_INLINE unsigned long SLockDCacheLines(unsigned long addr, unsigned long cnt)
Lock several D-Cache lines specified by address in S-Mode.
__STATIC_INLINE int32_t MFlushCCache(void)
Flush all Cluster Cache in M-Mode.
__STATIC_INLINE void SFlushDCacheLine(unsigned long addr)
Flush one D-Cache line specified by address in S-Mode.
__STATIC_INLINE unsigned long MLockICacheLines(unsigned long addr, unsigned long cnt)
Lock several I-Cache lines specified by address in M-Mode.
__STATIC_INLINE void MInvalICacheLines(unsigned long addr, unsigned long cnt)
Invalidate several I-Cache lines specified by address in M-Mode.
__STATIC_INLINE void SInvalICacheCCache(void)
Invalidate all I-Cache and Cluster Cache in S-Mode.
__STATIC_INLINE void SInvalCCache(void)
Invalidate all Cluster Cache in S-Mode.
__STATIC_INLINE void MInvalCCache(void)
Invalidate all Cluster Cache in M-Mode.
__STATIC_INLINE void UUnlockICacheLines(unsigned long addr, unsigned long cnt)
Unlock several I-Cache lines specified by address in U-Mode.
__STATIC_INLINE void MInvalICacheCCache(void)
Invalidate all I-Cache and Cluster Cache in M-Mode.
__STATIC_INLINE void MInvalICacheCCacheLines(unsigned long addr, unsigned long cnt)
Invalidate several I-Cache and Cluster Cache lines specified by address in M-Mode.
__STATIC_INLINE void MInvalICache(void)
Invalidate all I-Cache lines in M-Mode.
__STATIC_INLINE void UInvalICacheCCache(void)
Invalidate all I-Cache and Cluster Cache in U-Mode.
__STATIC_INLINE void MInvalICacheCCacheLine(unsigned long addr)
Invalidate one I-Cache and Cluster Cache line specified by address in M-Mode.
__STATIC_INLINE unsigned long ULockICacheLines(unsigned long addr, unsigned long cnt)
Lock several I-Cache lines specified by address in U-Mode.
__STATIC_INLINE void SInvalICacheLine(unsigned long addr)
Invalidate one I-Cache line specified by address in S-Mode.
__STATIC_INLINE unsigned long MLockICacheLine(unsigned long addr)
Lock one I-Cache line specified by address in M-Mode.
__STATIC_FORCEINLINE void DisableICache(void)
Disable ICache.
__STATIC_INLINE void UInvalICacheCCacheLine(unsigned long addr)
Invalidate one I-Cache and Cluster Cache line specified by address in U-Mode.
__STATIC_INLINE unsigned long ULockICacheLine(unsigned long addr)
Lock one I-Cache line specified by address in U-Mode.
__STATIC_FORCEINLINE void EnableICache(void)
Enable ICache.
__STATIC_INLINE int32_t ICachePresent(void)
Check ICache Unit Present or Not.
__STATIC_INLINE void SInvalICacheLines(unsigned long addr, unsigned long cnt)
Invalidate several I-Cache lines specified by address in S-Mode.
__STATIC_INLINE void UInvalICache(void)
Invalidate all I-Cache lines in U-Mode.
__STATIC_INLINE void MUnlockICacheLine(unsigned long addr)
Unlock one I-Cache line specified by address in M-Mode.
__STATIC_INLINE void UInvalICacheLines(unsigned long addr, unsigned long cnt)
Invalidate several I-Cache lines specified by address in U-Mode.
__STATIC_FORCEINLINE void EnableICacheECC(void)
Enable ICache ECC.
__STATIC_INLINE int32_t GetICacheInfo(CacheInfo_Type *info)
Get I-Cache Information.
__STATIC_INLINE void UUnlockICacheLine(unsigned long addr)
Unlock one I-Cache line specified by address in U-Mode.
__STATIC_FORCEINLINE void DisableICacheECC(void)
Disable ICache ECC.
__STATIC_INLINE void SInvalICacheCCacheLine(unsigned long addr)
Invalidate one I-Cache and Cluster Cache line specified by address in S-Mode.
__STATIC_INLINE void SUnlockICacheLines(unsigned long addr, unsigned long cnt)
Unlock several I-Cache lines specified by address in S-Mode.
__STATIC_INLINE void UInvalICacheLine(unsigned long addr)
Invalidate one I-Cache line specified by address in U-Mode.
__STATIC_INLINE unsigned long SLockICacheLine(unsigned long addr)
Lock one I-Cache line specified by address in S-Mode.
__STATIC_INLINE void MUnlockICacheLines(unsigned long addr, unsigned long cnt)
Unlock several I-Cache lines specified by address in M-Mode.
__STATIC_INLINE void UInvalCCache(void)
Invalidate all Cluster Cache in U-Mode.
__STATIC_INLINE void SInvalICache(void)
Invalidate all I-Cache lines in S-Mode.
__STATIC_INLINE void SUnlockICacheLine(unsigned long addr)
Unlock one I-Cache line specified by address in S-Mode.
__STATIC_INLINE unsigned long SLockICacheLines(unsigned long addr, unsigned long cnt)
Lock several I-Cache lines specified by address in S-Mode.
__STATIC_INLINE void UInvalICacheCCacheLines(unsigned long addr, unsigned long cnt)
Invalidate several I-Cache and Cluster Cache lines specified by address in U-Mode.
__STATIC_INLINE void MInvalICacheLine(unsigned long addr)
Invalidate one I-Cache line specified by address in M-Mode.
__STATIC_INLINE void SInvalICacheCCacheLines(unsigned long addr, unsigned long cnt)
Invalidate several I-Cache and Cluster Cache lines specified by address in S-Mode.
#define _FLD2VAL(field, value)
Mask and shift a register value to extract a bit filed value.
#define _VAL2FLD(field, value)
Mask and shift a bit field value for use in a register bit range.
#define __IM
Defines 'read only' structure member permissions.
#define __IOM
Defines 'read/write' structure member permissions.
Cache Information Type.
uint32_t setperway
Cache set per way.
uint32_t ways
Cache ways.
uint32_t linesize
Cache Line size in bytes.
uint32_t size
Cache total size in bytes.
Cluster Cache Control and Command Registers.
__IOM uint32_t CC_CTRL
Offset: 0x10 (R/W) Cluster Cache Control Register.
__IOM uint32_t CC_uCMD
Offset: 0xC4 (R/W) Cluster Cache U-mode Command Register.
__IOM uint32_t CC_INVALID_ALL
Offset: 0xDC (R/W) Cluster Cache Invalid All Register.
__IOM uint32_t CC_mCMD
Offset: 0x14 (R/W) Cluster Cache M-mode Command Register.
__IOM uint32_t CC_sCMD
Offset: 0xC0 (R/W) Cluster Cache S-mode Command Register.
Union type to access MDCFG_INFO CSR register.
rv_csr_t set
bit: 0..3 D-Cache sets per way
struct CSR_MDCFGINFO_Type::@16 b
Structure used for bit access.
rv_csr_t d
Type used for csr data access.
rv_csr_t lsize
bit: 7..9 D-Cache line size
rv_csr_t way
bit: 4..6 D-Cache way
Union type to access MICFG_INFO CSR register.
rv_csr_t d
Type used for csr data access.
rv_csr_t set
bit: 0..3 I-Cache sets per way
rv_csr_t lsize
bit: 7..9 I-Cache line size
struct CSR_MICFGINFO_Type::@15 b
Structure used for bit access.
rv_csr_t way
bit: 4..6 I-Cache way