PMP Functions

Functions that related to the RISCV Phyiscal Memory Protection. More...

Data Structures
struct	PMP_CONFIG

Functions
__STATIC_INLINE rv_csr_t	__get_PMPCFGx (uint32_t csr_idx)
	Get PMPCFGx Register by csr index. More...
__STATIC_INLINE void	__set_PMPCFGx (uint32_t csr_idx, rv_csr_t pmpcfg)
	Set PMPCFGx by csr index. More...
__STATIC_INLINE uint8_t	__get_PMPxCFG (uint32_t entry_idx)
	Get 8bit PMPxCFG Register by PMP entry index. More...
__STATIC_INLINE void	__set_PMPxCFG (uint32_t entry_idx, uint8_t pmpxcfg)
	Set 8bit PMPxCFG by pmp entry index. More...
__STATIC_INLINE rv_csr_t	__get_PMPADDRx (uint32_t csr_idx)
	Get PMPADDRx Register by CSR index. More...
__STATIC_INLINE void	__set_PMPADDRx (uint32_t csr_idx, rv_csr_t pmpaddr)
	Set PMPADDRx by CSR index. More...
__STATIC_INLINE void	__set_PMPENTRYx (uint32_t entry_idx, const pmp_config *pmp_cfg)
	Set PMP entry by entry idx. More...
__STATIC_INLINE int	__get_PMPENTRYx (unsigned int entry_idx, pmp_config *pmp_cfg)
	Get PMP entry by entry idx. More...

Detailed Description

Functions that related to the RISCV Phyiscal Memory Protection.

Optional physical memory protection (PMP) unit provides per-hart machine-mode control registers to allow physical memory access privileges (read, write, execute) to be specified for each physical memory region.

The PMP can supports region access control settings as small as four bytes.

Function Documentation

__get_PMPADDRx()

__STATIC_INLINE rv_csr_t __get_PMPADDRx

(

uint32_t

csr_idx

)

Get PMPADDRx Register by CSR index.

Return the content of the PMPADDRx Register.

Parameters

[in]

csr_idx

PMP region CSR index(0-15)

Returns

PMPADDRx Register value

Definition at line 206 of file core_feature_pmp.h.

{
    switch (csr_idx) {
        case 0: return __RV_CSR_READ(CSR_PMPADDR0);
        case 1: return __RV_CSR_READ(CSR_PMPADDR1);
        case 2: return __RV_CSR_READ(CSR_PMPADDR2);
        case 3: return __RV_CSR_READ(CSR_PMPADDR3);
        case 4: return __RV_CSR_READ(CSR_PMPADDR4);
        case 5: return __RV_CSR_READ(CSR_PMPADDR5);
        case 6: return __RV_CSR_READ(CSR_PMPADDR6);
        case 7: return __RV_CSR_READ(CSR_PMPADDR7);
        case 8: return __RV_CSR_READ(CSR_PMPADDR8);
        case 9: return __RV_CSR_READ(CSR_PMPADDR9);
        case 10: return __RV_CSR_READ(CSR_PMPADDR10);
        case 11: return __RV_CSR_READ(CSR_PMPADDR11);
        case 12: return __RV_CSR_READ(CSR_PMPADDR12);
        case 13: return __RV_CSR_READ(CSR_PMPADDR13);
        case 14: return __RV_CSR_READ(CSR_PMPADDR14);
        case 15: return __RV_CSR_READ(CSR_PMPADDR15);
        default: return 0;
    }
}

References __RV_CSR_READ, CSR_PMPADDR0, CSR_PMPADDR1, CSR_PMPADDR10, CSR_PMPADDR11, CSR_PMPADDR12, CSR_PMPADDR13, CSR_PMPADDR14, CSR_PMPADDR15, CSR_PMPADDR2, CSR_PMPADDR3, CSR_PMPADDR4, CSR_PMPADDR5, CSR_PMPADDR6, CSR_PMPADDR7, CSR_PMPADDR8, and CSR_PMPADDR9.

Referenced by __get_PMPENTRYx().

__get_PMPCFGx()

__STATIC_INLINE rv_csr_t __get_PMPCFGx

(

uint32_t

csr_idx

)

Get PMPCFGx Register by csr index.

Return the content of the PMPCFGx Register.

Parameters

[in]

csr_idx

PMPCFG CSR index(0-3)

Returns

PMPCFGx Register value

Remarks

• For RV64, only csr_idx = 0 and csr_idx = 2 is allowed. pmpcfg0 and pmpcfg2 hold the configurations for the 16 PMP entries, pmpcfg1 and pmpcfg3 are illegal
• For RV32, pmpcfg0–pmpcfg3, hold the configurations pmp0cfg–pmp15cfg for the 16 PMP entries

Definition at line 89 of file core_feature_pmp.h.

{
    switch (csr_idx) {
        case 0: return __RV_CSR_READ(CSR_PMPCFG0);
        case 1: return __RV_CSR_READ(CSR_PMPCFG1);
        case 2: return __RV_CSR_READ(CSR_PMPCFG2);
        case 3: return __RV_CSR_READ(CSR_PMPCFG3);
        default: return 0;
    }
}

References __RV_CSR_READ, CSR_PMPCFG0, CSR_PMPCFG1, CSR_PMPCFG2, and CSR_PMPCFG3.

Referenced by __get_PMPENTRYx(), __get_PMPxCFG(), __set_PMPENTRYx(), and __set_PMPxCFG().

__get_PMPENTRYx()

__STATIC_INLINE int __get_PMPENTRYx	(	unsigned int	entry_idx,
		pmp_config *	pmp_cfg
	)

Get PMP entry by entry idx.

Write the given value to the PMPxCFG Register and PMPADDRx.

Parameters

[in]	entry_idx	PMP entry index(0-15)
[out]	pmp_cfg	structure of L, X, W, R, A field of PMP configuration register, memory region base address and size of memory region as power of 2

Returns

-1 failure, else 0 success

Remarks

• If the size of memory region is 2^12(4KB) range, pmp_cfg->order makes 12, and the like.
• TOR of A field in PMP configuration register is not considered here.

Definition at line 330 of file core_feature_pmp.h.

{
    unsigned int cfg_shift, cfg_csr_idx, addr_csr_idx = 0;
    unsigned long cfgmask, pmpcfg, prot = 0;
    unsigned long t1, addr, pmpaddr, len = 0;
    uint8_t csr_cfg_num = 0;
    /* check parameters */
    if (entry_idx >= __PMP_ENTRY_NUM || !pmp_cfg) return -1;
 
    /* calculate PMP register and offset */
#if __RISCV_XLEN == 32
    csr_cfg_num = 4;
    cfg_csr_idx = entry_idx >> 2;
#elif __RISCV_XLEN == 64
    csr_cfg_num = 8;
    cfg_csr_idx = (entry_idx>> 2) & ~1;
#else
// TODO Add RV128 Handling
    return -1;
#endif
 
    cfg_shift = (entry_idx & (csr_cfg_num - 1)) << 3;
    addr_csr_idx = entry_idx;
 
    /* decode PMP config */
    cfgmask = (0xFFUL << cfg_shift);
    pmpcfg = (__get_PMPCFGx(cfg_csr_idx) & cfgmask);
    prot = pmpcfg >> cfg_shift;
 
    /* decode PMP address */
    pmpaddr = __get_PMPADDRx(addr_csr_idx);
    if (PMP_A_NAPOT == (prot & PMP_A)) {
        t1 = __CTZ(~pmpaddr);
        addr = (pmpaddr & ~((1UL << t1) - 1)) << PMP_SHIFT;
        len = (t1 + PMP_SHIFT + 1);
    } else {
        addr = pmpaddr << PMP_SHIFT;
        len = PMP_SHIFT;
    }
 
    /* return details */
    pmp_cfg->protection = prot;
    pmp_cfg->base_addr = addr;
    pmp_cfg->order = len;
 
    return 0;
}

References __CTZ(), __get_PMPADDRx(), __get_PMPCFGx(), PMP_A, PMP_A_NAPOT, and PMP_SHIFT.

__get_PMPxCFG()

__STATIC_INLINE uint8_t __get_PMPxCFG

(

uint32_t

entry_idx

)

Get 8bit PMPxCFG Register by PMP entry index.

Return the content of the PMPxCFG Register.

Parameters

[in]

entry_idx

PMP region index(0-15)

Returns

PMPxCFG Register value

Definition at line 129 of file core_feature_pmp.h.

{
    rv_csr_t pmpcfgx = 0;
    uint8_t csr_cfg_num = 0;
    uint16_t csr_idx = 0;
    uint16_t cfg_shift = 0;
 
    if (entry_idx >= __PMP_ENTRY_NUM) return 0;
 
#if __RISCV_XLEN == 32
    csr_cfg_num = 4;
    csr_idx = entry_idx >> 2;
#elif __RISCV_XLEN == 64
    csr_cfg_num = 8;
    /* For RV64, pmpcfg0 and pmpcfg2 each hold 8 PMP entries, align by 2 */
    csr_idx = (entry_idx >> 2) & ~1;
#else
    // TODO Add RV128 Handling
    return 0;
#endif
    pmpcfgx = __get_PMPCFGx(csr_idx);
    /*
     * first get specific pmpxcfg's order in one CSR composed of csr_cfg_num pmpxcfgs,
     * then get pmpxcfg's bit position in one CSR by left shift 3(each pmpxcfg size is one byte)
     */
    cfg_shift = (entry_idx & (csr_cfg_num - 1)) << 3;
 
    /* read specific pmpxcfg register value */
    return (uint8_t)(__RV_EXTRACT_FIELD(pmpcfgx, 0xFF << cfg_shift));
}

References __get_PMPCFGx().

__set_PMPADDRx()

__STATIC_INLINE void __set_PMPADDRx	(	uint32_t	csr_idx,
		rv_csr_t	pmpaddr
	)

Set PMPADDRx by CSR index.

Write the given value to the PMPADDRx Register.

Parameters

[in]	csr_idx	PMP region CSR index(0-15)
[in]	pmpaddr	PMPADDRx Register value to set

Definition at line 235 of file core_feature_pmp.h.

{
    switch (csr_idx) {
        case 0: __RV_CSR_WRITE(CSR_PMPADDR0, pmpaddr); break;
        case 1: __RV_CSR_WRITE(CSR_PMPADDR1, pmpaddr); break;
        case 2: __RV_CSR_WRITE(CSR_PMPADDR2, pmpaddr); break;
        case 3: __RV_CSR_WRITE(CSR_PMPADDR3, pmpaddr); break;
        case 4: __RV_CSR_WRITE(CSR_PMPADDR4, pmpaddr); break;
        case 5: __RV_CSR_WRITE(CSR_PMPADDR5, pmpaddr); break;
        case 6: __RV_CSR_WRITE(CSR_PMPADDR6, pmpaddr); break;
        case 7: __RV_CSR_WRITE(CSR_PMPADDR7, pmpaddr); break;
        case 8: __RV_CSR_WRITE(CSR_PMPADDR8, pmpaddr); break;
        case 9: __RV_CSR_WRITE(CSR_PMPADDR9, pmpaddr); break;
        case 10: __RV_CSR_WRITE(CSR_PMPADDR10, pmpaddr); break;
        case 11: __RV_CSR_WRITE(CSR_PMPADDR11, pmpaddr); break;
        case 12: __RV_CSR_WRITE(CSR_PMPADDR12, pmpaddr); break;
        case 13: __RV_CSR_WRITE(CSR_PMPADDR13, pmpaddr); break;
        case 14: __RV_CSR_WRITE(CSR_PMPADDR14, pmpaddr); break;
        case 15: __RV_CSR_WRITE(CSR_PMPADDR15, pmpaddr); break;
        default: return;
    }
}

References __RV_CSR_WRITE, CSR_PMPADDR0, CSR_PMPADDR1, CSR_PMPADDR10, CSR_PMPADDR11, CSR_PMPADDR12, CSR_PMPADDR13, CSR_PMPADDR14, CSR_PMPADDR15, CSR_PMPADDR2, CSR_PMPADDR3, CSR_PMPADDR4, CSR_PMPADDR5, CSR_PMPADDR6, CSR_PMPADDR7, CSR_PMPADDR8, and CSR_PMPADDR9.

Referenced by __set_PMPENTRYx().

__set_PMPCFGx()

__STATIC_INLINE void __set_PMPCFGx	(	uint32_t	csr_idx,
		rv_csr_t	pmpcfg
	)

Set PMPCFGx by csr index.

Write the given value to the PMPCFGx Register.

Parameters

[in]	csr_idx	PMPCFG CSR index(0-3)
[in]	pmpcfg	PMPCFGx Register value to set

Remarks

• For RV64, only csr_idx = 0 and csr_idx = 2 is allowed. pmpcfg0 and pmpcfg2 hold the configurations for the 16 PMP entries, pmpcfg1 and pmpcfg3 are illegal
• For RV32, pmpcfg0–pmpcfg3, hold the configurations pmp0cfg–pmp15cfg for the 16 PMP entries

Definition at line 112 of file core_feature_pmp.h.

{
    switch (csr_idx) {
        case 0: __RV_CSR_WRITE(CSR_PMPCFG0, pmpcfg); break;
        case 1: __RV_CSR_WRITE(CSR_PMPCFG1, pmpcfg); break;
        case 2: __RV_CSR_WRITE(CSR_PMPCFG2, pmpcfg); break;
        case 3: __RV_CSR_WRITE(CSR_PMPCFG3, pmpcfg); break;
        default: return;
    }
}

References __RV_CSR_WRITE, CSR_PMPCFG0, CSR_PMPCFG1, CSR_PMPCFG2, and CSR_PMPCFG3.

Referenced by __set_PMPENTRYx(), and __set_PMPxCFG().

__set_PMPENTRYx()

__STATIC_INLINE void __set_PMPENTRYx	(	uint32_t	entry_idx,
		const pmp_config *	pmp_cfg
	)

Set PMP entry by entry idx.

Write the given value to the PMPxCFG Register and PMPADDRx.

Parameters

[in]	entry_idx	PMP entry index(0-15)
[in]	pmp_cfg	structure of L, X, W, R field of PMP configuration register, memory region base address and size of memory region as power of 2

Remarks

• If the size of memory region is 2^12(4KB) range, pmp_cfg->order makes 12, and the like.
• Suppose the size of memory region is 2^X bytes range, if X >=3, the NA4 mode is not selectable, NAPOT is selected.
• TOR of A field in PMP configuration register is not considered here.

Definition at line 269 of file core_feature_pmp.h.

{
    unsigned int cfg_shift, cfg_csr_idx, addr_csr_idx = 0;
    unsigned long cfgmask, addrmask = 0;
    unsigned long pmpcfg, pmpaddr = 0;
    unsigned long protection, csr_cfg_num = 0;
    /* check parameters */
    if (entry_idx >= __PMP_ENTRY_NUM || pmp_cfg->order > __RISCV_XLEN || pmp_cfg->order < PMP_SHIFT) return;
 
    /* calculate PMP register and offset */
#if __RISCV_XLEN == 32
    csr_cfg_num = 4;
    cfg_csr_idx = (entry_idx >> 2);
#elif __RISCV_XLEN == 64
    csr_cfg_num = 8;
    cfg_csr_idx = ((entry_idx >> 2)) & ~1;
#else
    // TODO Add RV128 Handling
    return;
#endif
    /*
     * first get specific pmpxcfg's order in one CSR composed of csr_cfg_num pmpxcfgs,
     * then get pmpxcfg's bit position in one CSR by left shift 3, each pmpxcfg size is one byte
     */
    cfg_shift = (entry_idx & (csr_cfg_num - 1)) << 3;
    addr_csr_idx = entry_idx;
 
    /* encode PMP config */
    protection = (unsigned long)pmp_cfg->protection;
    protection |= (PMP_SHIFT == pmp_cfg->order) ? PMP_A_NA4 : PMP_A_NAPOT;
    cfgmask = ~(0xFFUL << cfg_shift);
    pmpcfg = (__get_PMPCFGx(cfg_csr_idx) & cfgmask);
    pmpcfg |= ((protection << cfg_shift) & ~cfgmask);
 
    /* encode PMP address */
    if (PMP_SHIFT == pmp_cfg->order) { /* NA4 */
        pmpaddr = (pmp_cfg->base_addr >> PMP_SHIFT);
    } else { /* NAPOT */
        addrmask = (1UL << (pmp_cfg->order - PMP_SHIFT)) - 1;
        pmpaddr = ((pmp_cfg->base_addr >> PMP_SHIFT) & ~addrmask);
        pmpaddr |= (addrmask >> 1);
    }
    /*
     * write csrs, update the address first, in case the entry is locked that
     * we won't be able to modify it after we set the config csr.
     */
    __set_PMPADDRx(addr_csr_idx, pmpaddr);
    __set_PMPCFGx(cfg_csr_idx, pmpcfg);
}

References __get_PMPCFGx(), __RISCV_XLEN, __set_PMPADDRx(), __set_PMPCFGx(), PMP_A_NA4, PMP_A_NAPOT, and PMP_SHIFT.

__set_PMPxCFG()

__STATIC_INLINE void __set_PMPxCFG	(	uint32_t	entry_idx,
		uint8_t	pmpxcfg
	)

Set 8bit PMPxCFG by pmp entry index.

Set the given pmpxcfg value to the PMPxCFG Register.

Parameters

[in]	entry_idx	PMPx region index(0-15)
[in]	pmpxcfg	PMPxCFG register value to set

Remarks

• For RV32, 4 pmpxcfgs are densely packed into one CSR in order For RV64, 8 pmpxcfgs are densely packed into one CSR in order

Definition at line 169 of file core_feature_pmp.h.

{
    rv_csr_t pmpcfgx = 0;
    uint8_t csr_cfg_num = 0;
    uint16_t csr_idx = 0;
    uint16_t cfg_shift = 0;
    if (entry_idx >= __PMP_ENTRY_NUM) return;
 
#if __RISCV_XLEN == 32
    csr_cfg_num = 4;
    csr_idx = entry_idx >> 2;
#elif __RISCV_XLEN == 64
    csr_cfg_num = 8;
    /* For RV64, pmpcfg0 and pmpcfg2 each hold 8 PMP entries, align by 2 */
    csr_idx = (entry_idx >> 2) & ~1;
#else
    // TODO Add RV128 Handling
    return;
#endif
    /* read specific pmpcfgx register value */
    pmpcfgx = __get_PMPCFGx(csr_idx);
    /*
     * first get specific pmpxcfg's order in one CSR composed of csr_cfg_num pmpxcfgs,
     * then get pmpxcfg's bit position in one CSR by left shift 3(each pmpxcfg size is one byte)
     */
    cfg_shift = (entry_idx & (csr_cfg_num - 1)) << 3;
 
    pmpcfgx = __RV_INSERT_FIELD(pmpcfgx, 0xFFUL << cfg_shift, pmpxcfg);
    __set_PMPCFGx(csr_idx, pmpcfgx);
}

References __get_PMPCFGx(), and __set_PMPCFGx().