NMSIS-Core
Version 1.3.1
NMSIS-Core support for Nuclei processor-based devices
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Type definitions and defines for core registers. More...
Modules | |
Base Register Define and Type Definitions | |
Type definitions and defines for base core registers. | |
Register Define and Type Definitions Of ECLIC | |
Type definitions and defines for eclic registers. | |
Register Define and Type Definitions Of System Timer | |
Type definitions and defines for system timer registers. | |
Macros | |
#define | __RISCV_XLEN 32 |
Refer to the width of an integer register in bits(either 32 or 64) More... | |
Typedefs | |
typedef unsigned long | rv_csr_t |
Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V. More... | |
Type definitions and defines for core registers.
#define __RISCV_XLEN 32 |
Refer to the width of an integer register in bits(either 32 or 64)
Definition at line 48 of file core_feature_base.h.
typedef unsigned long rv_csr_t |
Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V.
Definition at line 55 of file core_feature_base.h.