 |
NMSIS-Core
Version 1.5.0
NMSIS-Core support for Nuclei processor-based devices
|
|
NMSIS-Core
Version 1.5.0
NMSIS-Core support for Nuclei processor-based devices
|
Type definitions and defines for smpcc registers. More...
Data Structures | |
| union | SMP_VER_Type |
| Union type to access SMP_VER information register. More... | |
| union | SMP_CFG_Type |
| Union type to access SMP_CFG information register. More... | |
| union | CC_CFG_Type |
| Union type to access CC_CFG information register. More... | |
| union | SMP_ENB_Type |
| Union type to access SMP_ENB configure register. More... | |
| union | CC_CTRL_Type |
| Union type to access CC_CTRL configure register. More... | |
| union | CC_CMD_Type |
| Union type to access CC_CMD register. More... | |
| union | CC_ERR_INJ_Type |
| Union type to access CC_ERR_INJ register. More... | |
| union | CC_RECV_CNT_Type |
| Union type to access CC_RECV_CNT register. More... | |
| union | CC_FATAL_CNT_Type |
| Union type to access CC_FATAL_CNT register. More... | |
| union | CC_RECV_THV_Type |
| Union type to access CC_RECV_THV register. More... | |
| union | CC_FATAL_THV_Type |
| Union type to access CC_FATAL_THV register. More... | |
| union | CLIENT_ERR_STATUS_Type |
| Union type to access CLIENT_ERR_STATUS register. More... | |
| union | SNOOP_PENDING_Type |
| Union type to access SNOOP_PENDING register. More... | |
| union | TRANS_PENDING_Type |
| Union type to access TRANS_PENDING register. More... | |
| union | CLM_ADDR_BASE_Type |
| Union type to access CLM_ADDR_BASE register. More... | |
| union | CLM_WAY_EN_Type |
| Union type to access CLM_WAY_EN register. More... | |
| union | CC_INVALID_ALL_Type |
| Union type to access CC_INVALID_ALL register. More... | |
| union | STM_CTRL_Type |
| Union type to access STM_CTRL register. More... | |
| union | STM_CFG_Type |
| Union type to access STM_CFG register. More... | |
| union | STM_TIMEOUT_Type |
| Union type to access STM_TIMEOUT register. More... | |
| union | DFF_PROT_Type |
| Union type to access DFF_PROT register. More... | |
| union | ECC_ERR_MSK_Type |
| Union type to access ECC_ERR_MSK register. More... | |
| union | NS_RG_Type |
| Union type to access NS_RG register. More... | |
| union | SMP_PMON_SEL_Type |
| Union type to access SMP_PMON_SEL register. More... | |
| union | CLIENT_WAY_MASK_Type |
| Union type to access CLIENT_WAY_MASK register. More... | |
| struct | SMPCC_Type |
| Access to the structure of SMPCC Memory Map. More... | |
Macros | |
| #define | SMPCC_CTRL_CC_EN_Pos 0U |
| SMPCC CC_CTRL CC_EN Position. More... | |
| #define | SMPCC_CTRL_CC_EN_Msk (0x1UL << SMPCC_CTRL_CC_EN_Pos) |
| SMPCC CC_CTRL CC_EN Mask. More... | |
| #define | SMPCC_CTRL_CC_EN_ENABLE 1U |
| SMPCC CC_CTRL CC_EN Enable. More... | |
| #define | SMPCC_CTRL_CC_EN_DISABLE 0U |
| SMPCC CC_CTRL CC_EN Disable. More... | |
| #define | SMPCC_CTRL_CC_ECC_EN_Pos 1U |
| SMPCC CC_CTRL CC_ECC_EN Position. More... | |
| #define | SMPCC_CTRL_CC_ECC_EN_Msk (0x1UL << SMPCC_CTRL_CC_ECC_EN_Pos) |
| SMPCC CC_CTRL CC_ECC_EN Mask. More... | |
| #define | SMPCC_CTRL_CC_ECC_EN_ENABLE 1U |
| SMPCC CC_CTRL CC_ECC_EN Enable. More... | |
| #define | SMPCC_CTRL_CC_ECC_EN_DISABLE 0U |
| SMPCC CC_CTRL CC_ECC_EN Disable. More... | |
| #define | SMPCC_CTRL_CC_ECC_EXCP_EN_Pos 2U |
| SMPCC CC_CTRL ECC_EXCP_EN Position. More... | |
| #define | SMPCC_CTRL_CC_ECC_EXCP_EN_Msk (0x1UL << SMPCC_CTRL_CC_ECC_EXCP_EN_Pos) |
| SMPCC CC_CTRL ECC_EXCP_EN Mask. More... | |
| #define | SMPCC_CTRL_CC_ECC_EXCP_EN_ENABLE 1U |
| SMPCC CC_CTRL ECC_EXCP_EN Enable. More... | |
| #define | SMPCC_CTRL_CC_ECC_EXCP_EN_DISABLE 0U |
| SMPCC CC_CTRL ECC_EXCP_EN Disable. More... | |
| #define | SMPCC_CTRL_LOCK_ECC_CFG_Pos 3U |
| SMPCC CC_CTRL LOCK_ECC_CFG Position. More... | |
| #define | SMPCC_CTRL_LOCK_ECC_CFG_Msk (0x1UL << SMPCC_CTRL_LOCK_ECC_CFG_Pos) |
| SMPCC CC_CTRL LOCK_ECC_CFG Mask. More... | |
| #define | SMPCC_CTRL_LOCK_ECC_CFG_LOCK 1U |
| SMPCC CC_CTRL LOCK_ECC_CFG Lock. More... | |
| #define | SMPCC_CTRL_LOCK_ECC_ERR_INJ_Pos 4U |
| SMPCC CC_CTRL LOCK_ECC_ERR_INJ Position. More... | |
| #define | SMPCC_CTRL_LOCK_ECC_ERR_INJ_Msk (0x1UL << SMPCC_CTRL_LOCK_ECC_ERR_INJ_Pos) |
| SMPCC CC_CTRL LOCK_ECC_ERR_INJ Mask. More... | |
| #define | SMPCC_CTRL_LOCK_ECC_ERR_INJ_LOCK 1U |
| SMPCC CC_CTRL LOCK_ECC_ERR_INJ Lock. More... | |
| #define | SMPCC_CTRL_RECV_ERR_IRQ_EN_Pos 5U |
| SMPCC CC_CTRL RECV_ERR_IRQ_EN Position. More... | |
| #define | SMPCC_CTRL_RECV_ERR_IRQ_EN_Msk (0x1UL << SMPCC_CTRL_RECV_ERR_IRQ_EN_Pos) |
| SMPCC CC_CTRL RECV_ERR_IRQ_EN Mask. More... | |
| #define | SMPCC_CTRL_RECV_ERR_IRQ_EN_ENABLE 1U |
| SMPCC CC_CTRL RECV_ERR_IRQ_EN Enable. More... | |
| #define | SMPCC_CTRL_RECV_ERR_IRQ_EN_DISABLE 0U |
| SMPCC CC_CTRL RECV_ERR_IRQ_EN Disable. More... | |
| #define | SMPCC_CTRL_FATAL_ERR_IRQ_EN_Pos 6U |
| SMPCC CC_CTRL FATAL_ERR_IRQ_EN Position. More... | |
| #define | SMPCC_CTRL_FATAL_ERR_IRQ_EN_Msk (0x1UL << SMPCC_CTRL_FATAL_ERR_IRQ_EN_Pos) |
| SMPCC CC_CTRL FATAL_ERR_IRQ_EN Mask. More... | |
| #define | SMPCC_CTRL_FATAL_ERR_IRQ_EN_ENABLE 1U |
| SMPCC CC_CTRL FATAL_ERR_IRQ_EN Enable. More... | |
| #define | SMPCC_CTRL_FATAL_ERR_IRQ_EN_DISABLE 0U |
| SMPCC CC_CTRL FATAL_ERR_IRQ_EN Disable. More... | |
| #define | SMPCC_CTRL_BUS_ERR_PEND_Pos 7U |
| SMPCC CC_CTRL BUS_ERR_PEND Position. More... | |
| #define | SMPCC_CTRL_BUS_ERR_PEND_Msk (0x1UL << SMPCC_CTRL_BUS_ERR_PEND_Pos) |
| SMPCC CC_CTRL BUS_ERR_PEND Mask. More... | |
| #define | SMPCC_CTRL_BUS_ERR_IRQ_EN_Pos 8U |
| SMPCC CC_CTRL BUS_ERR_IRQ_EN Position. More... | |
| #define | SMPCC_CTRL_BUS_ERR_IRQ_EN_Msk (0x1UL << SMPCC_CTRL_BUS_ERR_IRQ_EN_Pos) |
| SMPCC CC_CTRL BUS_ERR_IRQ_EN Mask. More... | |
| #define | SMPCC_CTRL_BUS_ERR_IRQ_EN_ENABLE 1U |
| SMPCC CC_CTRL BUS_ERR_IRQ_EN Enable. More... | |
| #define | SMPCC_CTRL_BUS_ERR_IRQ_EN_DISABLE 0U |
| SMPCC CC_CTRL BUS_ERR_IRQ_EN Disable. More... | |
| #define | SMPCC_CTRL_SUP_CMD_EN_Pos 9U |
| SMPCC CC_CTRL SUP_CMD_EN Position. More... | |
| #define | SMPCC_CTRL_SUP_CMD_EN_Msk (0x1UL << SMPCC_CTRL_SUP_CMD_EN_Pos) |
| SMPCC CC_CTRL SUP_CMD_EN Mask. More... | |
| #define | SMPCC_CTRL_SUP_CMD_EN_ENABLE 1U |
| SMPCC CC_CTRL SUP_CMD_EN Enable. More... | |
| #define | SMPCC_CTRL_SUP_CMD_EN_DISABLE 0U |
| SMPCC CC_CTRL SUP_CMD_EN Disable. More... | |
| #define | SMPCC_CTRL_USE_CMD_EN_Pos 10U |
| SMPCC CC_CTRL USE_CMD_EN Position. More... | |
| #define | SMPCC_CTRL_USE_CMD_EN_Msk (0x1UL << SMPCC_CTRL_USE_CMD_EN_Pos) |
| SMPCC CC_CTRL USE_CMD_EN Mask. More... | |
| #define | SMPCC_CTRL_USE_CMD_EN_ENABLE 1U |
| SMPCC CC_CTRL USE_CMD_EN Enable. More... | |
| #define | SMPCC_CTRL_USE_CMD_EN_DISABLE 0U |
| SMPCC CC_CTRL USE_CMD_EN Disable. More... | |
| #define | SMPCC_CTRL_ECC_CHK_EN_Pos 11U |
| SMPCC CC_CTRL ECC_CHK_EN Position. More... | |
| #define | SMPCC_CTRL_ECC_CHK_EN_Msk (0x1UL << SMPCC_CTRL_ECC_CHK_EN_Pos) |
| SMPCC CC_CTRL ECC_CHK_EN Mask. More... | |
| #define | SMPCC_CTRL_ECC_CHK_EN_ENABLE 1U |
| SMPCC CC_CTRL ECC_CHK_EN Enable. More... | |
| #define | SMPCC_CTRL_ECC_CHK_EN_DISABLE 0U |
| SMPCC CC_CTRL ECC_CHK_EN Disable. More... | |
| #define | SMPCC_CTRL_CLM_ECC_EN_Pos 12U |
| SMPCC CC_CTRL CLM_ECC_EN Position. More... | |
| #define | SMPCC_CTRL_CLM_ECC_EN_Msk (0x1UL << SMPCC_CTRL_CLM_ECC_EN_Pos) |
| SMPCC CC_CTRL CLM_ECC_EN Mask. More... | |
| #define | SMPCC_CTRL_CLM_ECC_EN_ENABLE 1U |
| SMPCC CC_CTRL CLM_ECC_EN Enable. More... | |
| #define | SMPCC_CTRL_CLM_ECC_EN_DISABLE 0U |
| SMPCC CC_CTRL CLM_ECC_EN Disable. More... | |
| #define | SMPCC_CTRL_CLM_EXCP_EN_Pos 13U |
| SMPCC CC_CTRL CLM_EXCP_EN Position. More... | |
| #define | SMPCC_CTRL_CLM_EXCP_EN_Msk (0x1UL << SMPCC_CTRL_CLM_EXCP_EN_Pos) |
| SMPCC CC_CTRL CLM_EXCP_EN Mask. More... | |
| #define | SMPCC_CTRL_CLM_EXCP_EN_ENABLE 1U |
| SMPCC CC_CTRL CLM_EXCP_EN Enable. More... | |
| #define | SMPCC_CTRL_CLM_EXCP_EN_DISABLE 0U |
| SMPCC CC_CTRL CLM_EXCP_EN Disable. More... | |
| #define | SMPCC_CTRL_CLM_ECC_CHK_EN_Pos 14U |
| SMPCC CC_CTRL CLM_ECC_CHK_EN Position. More... | |
| #define | SMPCC_CTRL_CLM_ECC_CHK_EN_Msk (0x1UL << SMPCC_CTRL_CLM_ECC_CHK_EN_Pos) |
| SMPCC CC_CTRL CLM_ECC_CHK_EN Mask. More... | |
| #define | SMPCC_CTRL_CLM_ECC_CHK_EN_ENABLE 1U |
| SMPCC CC_CTRL CLM_ECC_CHK_EN Enable. More... | |
| #define | SMPCC_CTRL_CLM_ECC_CHK_EN_DISABLE 0U |
| SMPCC CC_CTRL CLM_ECC_CHK_EN Disable. More... | |
| #define | SMPCC_CTRL_PF_SH_CL_EN_Pos 15U |
| SMPCC CC_CTRL PF_SH_CL_EN Position. More... | |
| #define | SMPCC_CTRL_PF_SH_CL_EN_Msk (0x1UL << SMPCC_CTRL_PF_SH_CL_EN_Pos) |
| SMPCC CC_CTRL PF_SH_CL_EN Mask. More... | |
| #define | SMPCC_CTRL_PF_SH_CL_EN_ENABLE 1U |
| SMPCC CC_CTRL PF_SH_CL_EN Enable. More... | |
| #define | SMPCC_CTRL_PF_SH_CL_EN_DISABLE 0U |
| SMPCC CC_CTRL PF_SH_CL_EN Disable. More... | |
| #define | SMPCC_CTRL_PF_L2_EARLY_EN_Pos 16U |
| SMPCC CC_CTRL PF_L2_EARLY_EN Position. More... | |
| #define | SMPCC_CTRL_PF_L2_EARLY_EN_Msk (0x1UL << SMPCC_CTRL_PF_L2_EARLY_EN_Pos) |
| SMPCC CC_CTRL PF_L2_EARLY_EN Mask. More... | |
| #define | SMPCC_CTRL_PF_L2_EARLY_EN_ENABLE 1U |
| SMPCC CC_CTRL PF_L2_EARLY_EN Enable. More... | |
| #define | SMPCC_CTRL_PF_L2_EARLY_EN_DISABLE 0U |
| SMPCC CC_CTRL PF_L2_EARLY_EN Disable. More... | |
| #define | SMPCC_CTRL_PF_BIU_OUTS_EN_Pos 17U |
| SMPCC CC_CTRL PF_BIU_OUTS_EN Position. More... | |
| #define | SMPCC_CTRL_PF_BIU_OUTS_EN_Msk (0x1UL << SMPCC_CTRL_PF_BIU_OUTS_EN_Pos) |
| SMPCC CC_CTRL PF_BIU_OUTS_EN Mask. More... | |
| #define | SMPCC_CTRL_PF_BIU_OUTS_EN_ENABLE 1U |
| SMPCC CC_CTRL PF_BIU_OUTS_EN Enable. More... | |
| #define | SMPCC_CTRL_PF_BIU_OUTS_EN_DISABLE 0U |
| SMPCC CC_CTRL PF_BIU_OUTS_EN Disable. More... | |
| #define | SMPCC_CTRL_I_SNOOP_D_EN_Pos 18U |
| SMPCC CC_CTRL I_SNOOP_D_EN Position. More... | |
| #define | SMPCC_CTRL_I_SNOOP_D_EN_Msk (0x1UL << SMPCC_CTRL_I_SNOOP_D_EN_Pos) |
| SMPCC CC_CTRL I_SNOOP_D_EN Mask. More... | |
| #define | SMPCC_CTRL_I_SNOOP_D_EN_ENABLE 1U |
| SMPCC CC_CTRL I_SNOOP_D_EN Enable. More... | |
| #define | SMPCC_CTRL_I_SNOOP_D_EN_DISABLE 0U |
| SMPCC CC_CTRL I_SNOOP_D_EN Disable. More... | |
| #define | SMPCC_CTRL_IOCC_ERR_Pos 19U |
| SMPCC CC_CTRL IOCC_ERR Position. More... | |
| #define | SMPCC_CTRL_IOCC_ERR_Msk (0x1UL << SMPCC_CTRL_IOCC_ERR_Pos) |
| SMPCC CC_CTRL IOCC_ERR Mask. More... | |
| #define | SMPCC_CTRL_EARLY_WR_ERR_Pos 20U |
| SMPCC CC_CTRL EARLY_WR_ERR Position. More... | |
| #define | SMPCC_CTRL_EARLY_WR_ERR_Msk (0x1UL << SMPCC_CTRL_EARLY_WR_ERR_Pos) |
| SMPCC CC_CTRL EARLY_WR_ERR Mask. More... | |
| #define | SMPCC_CTRL_PF_NO_WB_Pos 21U |
| SMPCC CC_CTRL PF_NO_WB Position. More... | |
| #define | SMPCC_CTRL_PF_NO_WB_Msk (0x1UL << SMPCC_CTRL_PF_NO_WB_Pos) |
| SMPCC CC_CTRL PF_NO_WB Mask. More... | |
| #define | SMPCC_CTRL_PF_NO_WB_ENABLE 1U |
| SMPCC CC_CTRL PF_NO_WB Enable. More... | |
| #define | SMPCC_CTRL_PF_NO_WB_DISABLE 0U |
| SMPCC CC_CTRL PF_NO_WB Disable. More... | |
| #define | SMPCC_ERR_INJ_INJDATA_Pos 0U |
| SMPCC CC_ERR_INJ INJDATA Position. More... | |
| #define | SMPCC_ERR_INJ_INJDATA_Msk (0x1UL << SMPCC_ERR_INJ_INJDATA_Pos) |
| SMPCC CC_ERR_INJ INJDATA Mask. More... | |
| #define | SMPCC_ERR_INJ_INJDATA_ENABLE 1U |
| SMPCC CC_ERR_INJ INJDATA Enable. More... | |
| #define | SMPCC_ERR_INJ_INJDATA_DISABLE 0U |
| SMPCC CC_ERR_INJ INJDATA Disable. More... | |
| #define | SMPCC_ERR_INJ_INJTAG_Pos 1U |
| SMPCC CC_ERR_INJ INJTAG Position. More... | |
| #define | SMPCC_ERR_INJ_INJTAG_Msk (0x1UL << SMPCC_ERR_INJ_INJTAG_Pos) |
| SMPCC CC_ERR_INJ INJTAG Mask. More... | |
| #define | SMPCC_ERR_INJ_INJTAG_ENABLE 1U |
| SMPCC CC_ERR_INJ INJTAG Enable. More... | |
| #define | SMPCC_ERR_INJ_INJTAG_DISABLE 0U |
| SMPCC CC_ERR_INJ INJTAG Disable. More... | |
| #define | SMPCC_ERR_INJ_INJCLM_Pos 2U |
| SMPCC CC_ERR_INJ INJCLM Position. More... | |
| #define | SMPCC_ERR_INJ_INJCLM_Msk (0x1UL << SMPCC_ERR_INJ_INJCLM_Pos) |
| SMPCC CC_ERR_INJ INJCLM Mask. More... | |
| #define | SMPCC_ERR_INJ_INJCLM_ENABLE 1U |
| SMPCC CC_ERR_INJ INJCLM Enable. More... | |
| #define | SMPCC_ERR_INJ_INJCLM_DISABLE 0U |
| SMPCC CC_ERR_INJ INJCLM Disable. More... | |
| #define | SMPCC_ERR_INJ_INJMODE_Pos 3U |
| SMPCC CC_ERR_INJ INJMODE Position. More... | |
| #define | SMPCC_ERR_INJ_INJMODE_Msk (0x1UL << SMPCC_ERR_INJ_INJMODE_Pos) |
| SMPCC CC_ERR_INJ INJMODE Mask. More... | |
| #define | SMPCC_ERR_INJ_INJMODE_DIRECT 0U |
| SMPCC CC_ERR_INJ INJMODE Direct write mode. More... | |
| #define | SMPCC_ERR_INJ_INJMODE_XOR 1U |
| SMPCC CC_ERR_INJ INJMODE XOR write mode. More... | |
| #define | SMPCC_ERR_INJ_INJECCCODE_Pos 24U |
| SMPCC CC_ERR_INJ INJECCCODE Position. More... | |
| #define | SMPCC_ERR_INJ_INJECCCODE_Msk (0xFFUL << SMPCC_ERR_INJ_INJECCCODE_Pos) |
| SMPCC CC_ERR_INJ INJECCCODE Mask. More... | |
| #define | SMPCC_CLIERRSTS_READ_BUS_ERR_Pos 0U |
| SMPCC CLIENT ERROR STATUS READ_BUS_ERR Position. More... | |
| #define | SMPCC_CLIERRSTS_READ_BUS_ERR_Msk (0x1UL << SMPCC_CLIERRSTS_READ_BUS_ERR_Pos) |
| SMPCC CLIENT ERROR STATUS READ_BUS_ERR Mask. More... | |
| #define | SMPCC_CLIERRSTS_WRITE_BUS_ERR_Pos 1U |
| SMPCC CLIENT ERROR STATUS WRITE_BUS_ERR Position. More... | |
| #define | SMPCC_CLIERRSTS_WRITE_BUS_ERR_Msk (0x1UL << SMPCC_CLIERRSTS_WRITE_BUS_ERR_Pos) |
| SMPCC CLIENT ERROR STATUS WRITE_BUS_ERR Mask. More... | |
| #define | SMPCC_CLIERRSTS_CC_SCU_ECC_ERR_Pos 2U |
| SMPCC CLIENT ERROR STATUS CC_SCU_ECC_ERR Position. More... | |
| #define | SMPCC_CLIERRSTS_CC_SCU_ECC_ERR_Msk (0x1UL << SMPCC_CLIERRSTS_CC_SCU_ECC_ERR_Pos) |
| SMPCC CLIENT ERROR STATUS CC_SCU_ECC_ERR Mask. More... | |
| #define | SMPCC_CLIERRSTS_IOCP_BUS_ERR_Pos 3U |
| SMPCC CLIENT ERROR STATUS IOCP_BUS_ERR Position. More... | |
| #define | SMPCC_CLIERRSTS_IOCP_BUS_ERR_Msk (0x1UL << SMPCC_CLIERRSTS_IOCP_BUS_ERR_Pos) |
| SMPCC CLIENT ERROR STATUS IOCP_BUS_ERR Mask. More... | |
| #define | SMPCC_STMCTRL_RD_STM_EN_Pos 0U |
| SMPCC READ Stream Enable Position. More... | |
| #define | SMPCC_STMCTRL_RD_STM_EN_Msk (0x1UL << SMPCC_STMCTRL_RD_STM_EN_Pos) |
| SMPCC READ Stream Enable Mask. More... | |
| #define | SMPCC_STMCTRL_RD_STM_EN_ENABLE 1U |
| SMPCC READ Stream Enable Enable. More... | |
| #define | SMPCC_STMCTRL_RD_STM_EN_DISABLE 0U |
| SMPCC READ Stream Enable Disable. More... | |
| #define | SMPCC_STMCTRL_WR_STM_EN_Pos 1U |
| SMPCC WRITE Stream Enable Position. More... | |
| #define | SMPCC_STMCTRL_WR_STM_EN_Msk (0x1UL << SMPCC_STMCTRL_WR_STM_EN_Pos) |
| SMPCC WRITE Stream Enable Mask. More... | |
| #define | SMPCC_STMCTRL_WR_STM_EN_ENABLE 1U |
| SMPCC WRITE Stream Enable Enable. More... | |
| #define | SMPCC_STMCTRL_WR_STM_EN_DISABLE 0U |
| SMPCC WRITE Stream Enable Disable. More... | |
| #define | SMPCC_STMCTRL_TRANS_ALLOC_Pos 2U |
| SMPCC TRANSLATE ALLOC ATTRIBUTE Enable Position. More... | |
| #define | SMPCC_STMCTRL_TRANS_ALLOC_Msk (0x1UL << SMPCC_STMCTRL_TRANS_ALLOC_Pos) |
| SMPCC TRANSLATE ALLOC ATTRIBUTE Enable Mask. More... | |
| #define | SMPCC_STMCTRL_TRANS_ALLOC_ENABLE 1U |
| SMPCC TRANSLATE ALLOC ATTRIBUTE Enable. More... | |
| #define | SMPCC_STMCTRL_TRANS_ALLOC_DISABLE 0U |
| SMPCC TRANSLATE ALLOC ATTRIBUTE Disable. More... | |
| #define | SMPCC_STMCTRL_RD_MERGE_EN_Pos 3U |
| SMPCC READ Merge Enable Position. More... | |
| #define | SMPCC_STMCTRL_RD_MERGE_EN_Msk (0x1UL << SMPCC_STMCTRL_RD_MERGE_EN_Pos) |
| SMPCC READ Merge Enable Mask. More... | |
| #define | SMPCC_STMCTRL_RD_MERGE_EN_ENABLE 1U |
| SMPCC READ Merge Enable Enable. More... | |
| #define | SMPCC_STMCTRL_RD_MERGE_EN_DISABLE 0U |
| SMPCC READ Merge Enable Disable. More... | |
| #define | SMPCC_STMCTRL_CROSS_EN_Pos 4U |
| SMPCC READ STREAM CROSS 4K Enable Position. More... | |
| #define | SMPCC_STMCTRL_CROSS_EN_Msk (0x1UL << SMPCC_STMCTRL_CROSS_EN_Pos) |
| SMPCC READ STREAM CROSS 4K Enable Mask. More... | |
| #define | SMPCC_STMCTRL_CROSS_EN_ENABLE 1U |
| SMPCC READ STREAM CROSS 4K Enable. More... | |
| #define | SMPCC_STMCTRL_CROSS_EN_DISABLE 0U |
| SMPCC READ STREAM CROSS 4K Disable. More... | |
| #define | SMPCC_STMCFG_RD_BYTE_THRE_Pos 0U |
| SMPCC READ BYTE THRESHOLD Position. More... | |
| #define | SMPCC_STMCFG_RD_BYTE_THRE_Msk (0x3FFUL << SMPCC_STMCFG_RD_BYTE_THRE_Pos) |
| SMPCC READ BYTE THRESHOLD Mask. More... | |
| #define | SMPCC_STMCFG_RD_DEGREE_Pos 12U |
| SMPCC READ DEGREE Position. More... | |
| #define | SMPCC_STMCFG_RD_DEGREE_Msk (0x7UL << SMPCC_STMCFG_RD_DEGREE_Pos) |
| SMPCC READ DEGREE Mask. More... | |
| #define | SMPCC_STMCFG_RD_DISTANCE_Pos 16U |
| SMPCC READ DISTANCE Position. More... | |
| #define | SMPCC_STMCFG_RD_DISTANCE_Msk (0x7UL << SMPCC_STMCFG_RD_DISTANCE_Pos) |
| SMPCC READ DISTANCE Mask. More... | |
| #define | SMPCC_STMCFG_WR_BYTE_THRE_Pos 20U |
| SMPCC WRITE BYTE THRESHOLD Position. More... | |
| #define | SMPCC_STMCFG_WR_BYTE_THRE_Msk (0x7FFUL << SMPCC_STMCFG_WR_BYTE_THRE_Pos) |
| SMPCC WRITE BYTE THRESHOLD Mask. More... | |
| #define | SMPCC_DFF_PROT_CHK_EN_Pos 0U |
| SMPCC DFF PROTECT CHECK ENABLE Position. More... | |
| #define | SMPCC_DFF_PROT_CHK_EN_Msk (0x3UL << SMPCC_DFF_PROT_CHK_EN_Pos) |
| SMPCC DFF PROTECT CHECK ENABLE Mask. More... | |
| #define | SMPCC_DFF_PROT_CHK_EN_ENABLE 2U |
| SMPCC DFF PROTECT CHECK ENABLE ENABLE. More... | |
| #define | SMPCC_DFF_PROT_CHK_EN_DISABLE 1U |
| SMPCC DFF PROTECT CHECK ENABLE DISABLE. More... | |
| #define | SMPCC_NS_RG_CFG_Pos 0U |
| SMPCC Non-Shareable Region CFG Position. More... | |
| #define | SMPCC_NS_RG_CFG_Msk (0x3UL << SMPCC_NS_RG_CFG_Pos) |
| SMPCC Non-Shareable Region CFG Mask. More... | |
| #define | SMPCC_NS_RG_CFG_DISABLE 0x00U |
| SMPCC Non-Shareable Region CFG DISABLE. More... | |
| #define | SMPCC_NS_RG_CFG_NACL 0x10U |
| SMPCC Non-Shareable Region CFG NACL. More... | |
| #define | SMPCC_NS_RG_CFG_NAPOT 0x11U |
| SMPCC Non-Shareable Region CFG NAPOT. More... | |
| #define | SMPCC_PMON_EVENT_SEL_Pos 0U |
| SMPCC PMON EVENT SEL Position. More... | |
| #define | SMPCC_PMON_EVENT_SEL_Msk (0xFFFFUL << SMPCC_PMON_EVENT_SEL_Pos) |
| SMPCC PMON EVENT SEL Mask. More... | |
| #define | SMPCC_PMON_EVENT_DISABLE 0U |
| SMPCC PMON EVENT DISABLE. More... | |
| #define | SMPCC_PMON_EVENT_DATA_READ_COUNT 1U |
| SMPCC PMON EVENT DATA READ COUNT. More... | |
| #define | SMPCC_PMON_EVENT_DATA_WRITE_COUNT 2U |
| SMPCC PMON EVENT DATA WRITE COUNT SABLE. More... | |
| #define | SMPCC_PMON_EVENT_INSTR_READ_COUNT 3U |
| SMPCC PMON EVENT INSTR READ COUNT. More... | |
| #define | SMPCC_PMON_EVENT_DATA_READ_HIT_COUNT 4U |
| SMPCC PMON EVENT DATA READ HIT COUNT. More... | |
| #define | SMPCC_PMON_EVENT_DATA_WRITE_REPLACE_COUNT 5U |
| SMPCC PMON EVENT DATA WRITE REPLACE COUNT. More... | |
| #define | SMPCC_PMON_EVENT_DATA_READ_REPLACE_COUNT 6U |
| SMPCC PMON EVENT DATA READ REPLACE COUNT. More... | |
| #define | SMPCC_PMON_EVENT_DATA_READ_MISS_COUNT 7U |
| SMPCC PMON EVENT DATA READ MISS COUNT. More... | |
| #define | SMPCC_PMON_EVENT_INSTR_READ_HIT_COUNT 8U |
| SMPCC PMON EVENT INSTR READ HIT COUNT. More... | |
| #define | SMPCC_PMON_EVENT_INSTR_READ_MISS_COUNT 9U |
| SMPCC PMON EVENT INSTR READ MISS COUNT. More... | |
| #define | SMPCC_PMON_EVENT_INSTR_READ_REPLACE_COUNT 10U |
| SMPCC PMON EVENT INSTR READ REPLACE COUNT. More... | |
| #define | SMPCC_PMON_CLIENT_SEL_Pos 16U |
| SMPCC PMON CLIENT SEL Position. More... | |
| #define | SMPCC_PMON_CLIENT_SEL_Msk (0x1FUL << SMPCC_PMON_CLIENT_SEL_Pos) |
| SMPCC PMON CLIENT SEL Mask. More... | |
| #define | SMPCC_PMON_EVENT(event, client) |
| #define | SMPCC_BASE __SMPCC_BASEADDR |
| SMPCC Base Address. More... | |
| #define | SMPCC ((SMPCC_Type *)SMPCC_BASE) |
| SMPCC configuration struct. More... | |
Typedefs | |
| typedef __IO uint64_t | CC_BUS_ERR_ADDR_Type |
| Type to access CC_BUS_ERR_ADDR register. More... | |
| typedef __IO uint64_t | SMP_PMON_CNT_Type |
| Type to access SMP_PMON_CNT register. More... | |
| typedef __IO uint64_t | CLIENT_ERR_ADDR_Type |
| Type to access CLIENT_ERR_ADDR register. More... | |
Type definitions and defines for smpcc registers.
| #define SMPCC ((SMPCC_Type *)SMPCC_BASE) |
SMPCC configuration struct.
Definition at line 683 of file core_feature_smpcc.h.
| #define SMPCC_BASE __SMPCC_BASEADDR |
SMPCC Base Address.
Definition at line 682 of file core_feature_smpcc.h.
| #define SMPCC_CLIERRSTS_CC_SCU_ECC_ERR_Msk (0x1UL << SMPCC_CLIERRSTS_CC_SCU_ECC_ERR_Pos) |
SMPCC CLIENT ERROR STATUS CC_SCU_ECC_ERR Mask.
Definition at line 381 of file core_feature_smpcc.h.
| #define SMPCC_CLIERRSTS_CC_SCU_ECC_ERR_Pos 2U |
SMPCC CLIENT ERROR STATUS CC_SCU_ECC_ERR Position.
Definition at line 380 of file core_feature_smpcc.h.
| #define SMPCC_CLIERRSTS_IOCP_BUS_ERR_Msk (0x1UL << SMPCC_CLIERRSTS_IOCP_BUS_ERR_Pos) |
SMPCC CLIENT ERROR STATUS IOCP_BUS_ERR Mask.
Definition at line 384 of file core_feature_smpcc.h.
| #define SMPCC_CLIERRSTS_IOCP_BUS_ERR_Pos 3U |
SMPCC CLIENT ERROR STATUS IOCP_BUS_ERR Position.
Definition at line 383 of file core_feature_smpcc.h.
| #define SMPCC_CLIERRSTS_READ_BUS_ERR_Msk (0x1UL << SMPCC_CLIERRSTS_READ_BUS_ERR_Pos) |
SMPCC CLIENT ERROR STATUS READ_BUS_ERR Mask.
Definition at line 375 of file core_feature_smpcc.h.
| #define SMPCC_CLIERRSTS_READ_BUS_ERR_Pos 0U |
SMPCC CLIENT ERROR STATUS READ_BUS_ERR Position.
Definition at line 374 of file core_feature_smpcc.h.
| #define SMPCC_CLIERRSTS_WRITE_BUS_ERR_Msk (0x1UL << SMPCC_CLIERRSTS_WRITE_BUS_ERR_Pos) |
SMPCC CLIENT ERROR STATUS WRITE_BUS_ERR Mask.
Definition at line 378 of file core_feature_smpcc.h.
| #define SMPCC_CLIERRSTS_WRITE_BUS_ERR_Pos 1U |
SMPCC CLIENT ERROR STATUS WRITE_BUS_ERR Position.
Definition at line 377 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_BUS_ERR_IRQ_EN_DISABLE 0U |
SMPCC CC_CTRL BUS_ERR_IRQ_EN Disable.
Definition at line 182 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_BUS_ERR_IRQ_EN_ENABLE 1U |
SMPCC CC_CTRL BUS_ERR_IRQ_EN Enable.
Definition at line 181 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_BUS_ERR_IRQ_EN_Msk (0x1UL << SMPCC_CTRL_BUS_ERR_IRQ_EN_Pos) |
SMPCC CC_CTRL BUS_ERR_IRQ_EN Mask.
Definition at line 180 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_BUS_ERR_IRQ_EN_Pos 8U |
SMPCC CC_CTRL BUS_ERR_IRQ_EN Position.
Definition at line 179 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_BUS_ERR_PEND_Msk (0x1UL << SMPCC_CTRL_BUS_ERR_PEND_Pos) |
SMPCC CC_CTRL BUS_ERR_PEND Mask.
Definition at line 177 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_BUS_ERR_PEND_Pos 7U |
SMPCC CC_CTRL BUS_ERR_PEND Position.
Definition at line 176 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CC_ECC_EN_DISABLE 0U |
SMPCC CC_CTRL CC_ECC_EN Disable.
Definition at line 151 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CC_ECC_EN_ENABLE 1U |
SMPCC CC_CTRL CC_ECC_EN Enable.
Definition at line 150 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CC_ECC_EN_Msk (0x1UL << SMPCC_CTRL_CC_ECC_EN_Pos) |
SMPCC CC_CTRL CC_ECC_EN Mask.
Definition at line 149 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CC_ECC_EN_Pos 1U |
SMPCC CC_CTRL CC_ECC_EN Position.
Definition at line 148 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CC_ECC_EXCP_EN_DISABLE 0U |
SMPCC CC_CTRL ECC_EXCP_EN Disable.
Definition at line 156 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CC_ECC_EXCP_EN_ENABLE 1U |
SMPCC CC_CTRL ECC_EXCP_EN Enable.
Definition at line 155 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CC_ECC_EXCP_EN_Msk (0x1UL << SMPCC_CTRL_CC_ECC_EXCP_EN_Pos) |
SMPCC CC_CTRL ECC_EXCP_EN Mask.
Definition at line 154 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CC_ECC_EXCP_EN_Pos 2U |
SMPCC CC_CTRL ECC_EXCP_EN Position.
Definition at line 153 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CC_EN_DISABLE 0U |
SMPCC CC_CTRL CC_EN Disable.
Definition at line 146 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CC_EN_ENABLE 1U |
SMPCC CC_CTRL CC_EN Enable.
Definition at line 145 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CC_EN_Msk (0x1UL << SMPCC_CTRL_CC_EN_Pos) |
SMPCC CC_CTRL CC_EN Mask.
Definition at line 144 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CC_EN_Pos 0U |
SMPCC CC_CTRL CC_EN Position.
Definition at line 143 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CLM_ECC_CHK_EN_DISABLE 0U |
SMPCC CC_CTRL CLM_ECC_CHK_EN Disable.
Definition at line 212 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CLM_ECC_CHK_EN_ENABLE 1U |
SMPCC CC_CTRL CLM_ECC_CHK_EN Enable.
Definition at line 211 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CLM_ECC_CHK_EN_Msk (0x1UL << SMPCC_CTRL_CLM_ECC_CHK_EN_Pos) |
SMPCC CC_CTRL CLM_ECC_CHK_EN Mask.
Definition at line 210 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CLM_ECC_CHK_EN_Pos 14U |
SMPCC CC_CTRL CLM_ECC_CHK_EN Position.
Definition at line 209 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CLM_ECC_EN_DISABLE 0U |
SMPCC CC_CTRL CLM_ECC_EN Disable.
Definition at line 202 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CLM_ECC_EN_ENABLE 1U |
SMPCC CC_CTRL CLM_ECC_EN Enable.
Definition at line 201 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CLM_ECC_EN_Msk (0x1UL << SMPCC_CTRL_CLM_ECC_EN_Pos) |
SMPCC CC_CTRL CLM_ECC_EN Mask.
Definition at line 200 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CLM_ECC_EN_Pos 12U |
SMPCC CC_CTRL CLM_ECC_EN Position.
Definition at line 199 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CLM_EXCP_EN_DISABLE 0U |
SMPCC CC_CTRL CLM_EXCP_EN Disable.
Definition at line 207 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CLM_EXCP_EN_ENABLE 1U |
SMPCC CC_CTRL CLM_EXCP_EN Enable.
Definition at line 206 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CLM_EXCP_EN_Msk (0x1UL << SMPCC_CTRL_CLM_EXCP_EN_Pos) |
SMPCC CC_CTRL CLM_EXCP_EN Mask.
Definition at line 205 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_CLM_EXCP_EN_Pos 13U |
SMPCC CC_CTRL CLM_EXCP_EN Position.
Definition at line 204 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_EARLY_WR_ERR_Msk (0x1UL << SMPCC_CTRL_EARLY_WR_ERR_Pos) |
SMPCC CC_CTRL EARLY_WR_ERR Mask.
Definition at line 238 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_EARLY_WR_ERR_Pos 20U |
SMPCC CC_CTRL EARLY_WR_ERR Position.
Definition at line 237 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_ECC_CHK_EN_DISABLE 0U |
SMPCC CC_CTRL ECC_CHK_EN Disable.
Definition at line 197 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_ECC_CHK_EN_ENABLE 1U |
SMPCC CC_CTRL ECC_CHK_EN Enable.
Definition at line 196 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_ECC_CHK_EN_Msk (0x1UL << SMPCC_CTRL_ECC_CHK_EN_Pos) |
SMPCC CC_CTRL ECC_CHK_EN Mask.
Definition at line 195 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_ECC_CHK_EN_Pos 11U |
SMPCC CC_CTRL ECC_CHK_EN Position.
Definition at line 194 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_FATAL_ERR_IRQ_EN_DISABLE 0U |
SMPCC CC_CTRL FATAL_ERR_IRQ_EN Disable.
Definition at line 174 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_FATAL_ERR_IRQ_EN_ENABLE 1U |
SMPCC CC_CTRL FATAL_ERR_IRQ_EN Enable.
Definition at line 173 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_FATAL_ERR_IRQ_EN_Msk (0x1UL << SMPCC_CTRL_FATAL_ERR_IRQ_EN_Pos) |
SMPCC CC_CTRL FATAL_ERR_IRQ_EN Mask.
Definition at line 172 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_FATAL_ERR_IRQ_EN_Pos 6U |
SMPCC CC_CTRL FATAL_ERR_IRQ_EN Position.
Definition at line 171 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_I_SNOOP_D_EN_DISABLE 0U |
SMPCC CC_CTRL I_SNOOP_D_EN Disable.
Definition at line 232 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_I_SNOOP_D_EN_ENABLE 1U |
SMPCC CC_CTRL I_SNOOP_D_EN Enable.
Definition at line 231 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_I_SNOOP_D_EN_Msk (0x1UL << SMPCC_CTRL_I_SNOOP_D_EN_Pos) |
SMPCC CC_CTRL I_SNOOP_D_EN Mask.
Definition at line 230 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_I_SNOOP_D_EN_Pos 18U |
SMPCC CC_CTRL I_SNOOP_D_EN Position.
Definition at line 229 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_IOCC_ERR_Msk (0x1UL << SMPCC_CTRL_IOCC_ERR_Pos) |
SMPCC CC_CTRL IOCC_ERR Mask.
Definition at line 235 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_IOCC_ERR_Pos 19U |
SMPCC CC_CTRL IOCC_ERR Position.
Definition at line 234 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_LOCK_ECC_CFG_LOCK 1U |
SMPCC CC_CTRL LOCK_ECC_CFG Lock.
Definition at line 160 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_LOCK_ECC_CFG_Msk (0x1UL << SMPCC_CTRL_LOCK_ECC_CFG_Pos) |
SMPCC CC_CTRL LOCK_ECC_CFG Mask.
Definition at line 159 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_LOCK_ECC_CFG_Pos 3U |
SMPCC CC_CTRL LOCK_ECC_CFG Position.
Definition at line 158 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_LOCK_ECC_ERR_INJ_LOCK 1U |
SMPCC CC_CTRL LOCK_ECC_ERR_INJ Lock.
Definition at line 164 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_LOCK_ECC_ERR_INJ_Msk (0x1UL << SMPCC_CTRL_LOCK_ECC_ERR_INJ_Pos) |
SMPCC CC_CTRL LOCK_ECC_ERR_INJ Mask.
Definition at line 163 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_LOCK_ECC_ERR_INJ_Pos 4U |
SMPCC CC_CTRL LOCK_ECC_ERR_INJ Position.
Definition at line 162 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_BIU_OUTS_EN_DISABLE 0U |
SMPCC CC_CTRL PF_BIU_OUTS_EN Disable.
Definition at line 227 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_BIU_OUTS_EN_ENABLE 1U |
SMPCC CC_CTRL PF_BIU_OUTS_EN Enable.
Definition at line 226 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_BIU_OUTS_EN_Msk (0x1UL << SMPCC_CTRL_PF_BIU_OUTS_EN_Pos) |
SMPCC CC_CTRL PF_BIU_OUTS_EN Mask.
Definition at line 225 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_BIU_OUTS_EN_Pos 17U |
SMPCC CC_CTRL PF_BIU_OUTS_EN Position.
Definition at line 224 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_L2_EARLY_EN_DISABLE 0U |
SMPCC CC_CTRL PF_L2_EARLY_EN Disable.
Definition at line 222 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_L2_EARLY_EN_ENABLE 1U |
SMPCC CC_CTRL PF_L2_EARLY_EN Enable.
Definition at line 221 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_L2_EARLY_EN_Msk (0x1UL << SMPCC_CTRL_PF_L2_EARLY_EN_Pos) |
SMPCC CC_CTRL PF_L2_EARLY_EN Mask.
Definition at line 220 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_L2_EARLY_EN_Pos 16U |
SMPCC CC_CTRL PF_L2_EARLY_EN Position.
Definition at line 219 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_NO_WB_DISABLE 0U |
SMPCC CC_CTRL PF_NO_WB Disable.
Definition at line 243 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_NO_WB_ENABLE 1U |
SMPCC CC_CTRL PF_NO_WB Enable.
Definition at line 242 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_NO_WB_Msk (0x1UL << SMPCC_CTRL_PF_NO_WB_Pos) |
SMPCC CC_CTRL PF_NO_WB Mask.
Definition at line 241 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_NO_WB_Pos 21U |
SMPCC CC_CTRL PF_NO_WB Position.
Definition at line 240 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_SH_CL_EN_DISABLE 0U |
SMPCC CC_CTRL PF_SH_CL_EN Disable.
Definition at line 217 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_SH_CL_EN_ENABLE 1U |
SMPCC CC_CTRL PF_SH_CL_EN Enable.
Definition at line 216 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_SH_CL_EN_Msk (0x1UL << SMPCC_CTRL_PF_SH_CL_EN_Pos) |
SMPCC CC_CTRL PF_SH_CL_EN Mask.
Definition at line 215 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_PF_SH_CL_EN_Pos 15U |
SMPCC CC_CTRL PF_SH_CL_EN Position.
Definition at line 214 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_RECV_ERR_IRQ_EN_DISABLE 0U |
SMPCC CC_CTRL RECV_ERR_IRQ_EN Disable.
Definition at line 169 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_RECV_ERR_IRQ_EN_ENABLE 1U |
SMPCC CC_CTRL RECV_ERR_IRQ_EN Enable.
Definition at line 168 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_RECV_ERR_IRQ_EN_Msk (0x1UL << SMPCC_CTRL_RECV_ERR_IRQ_EN_Pos) |
SMPCC CC_CTRL RECV_ERR_IRQ_EN Mask.
Definition at line 167 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_RECV_ERR_IRQ_EN_Pos 5U |
SMPCC CC_CTRL RECV_ERR_IRQ_EN Position.
Definition at line 166 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_SUP_CMD_EN_DISABLE 0U |
SMPCC CC_CTRL SUP_CMD_EN Disable.
Definition at line 187 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_SUP_CMD_EN_ENABLE 1U |
SMPCC CC_CTRL SUP_CMD_EN Enable.
Definition at line 186 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_SUP_CMD_EN_Msk (0x1UL << SMPCC_CTRL_SUP_CMD_EN_Pos) |
SMPCC CC_CTRL SUP_CMD_EN Mask.
Definition at line 185 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_SUP_CMD_EN_Pos 9U |
SMPCC CC_CTRL SUP_CMD_EN Position.
Definition at line 184 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_USE_CMD_EN_DISABLE 0U |
SMPCC CC_CTRL USE_CMD_EN Disable.
Definition at line 192 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_USE_CMD_EN_ENABLE 1U |
SMPCC CC_CTRL USE_CMD_EN Enable.
Definition at line 191 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_USE_CMD_EN_Msk (0x1UL << SMPCC_CTRL_USE_CMD_EN_Pos) |
SMPCC CC_CTRL USE_CMD_EN Mask.
Definition at line 190 of file core_feature_smpcc.h.
| #define SMPCC_CTRL_USE_CMD_EN_Pos 10U |
SMPCC CC_CTRL USE_CMD_EN Position.
Definition at line 189 of file core_feature_smpcc.h.
| #define SMPCC_DFF_PROT_CHK_EN_DISABLE 1U |
SMPCC DFF PROTECT CHECK ENABLE DISABLE.
Definition at line 545 of file core_feature_smpcc.h.
| #define SMPCC_DFF_PROT_CHK_EN_ENABLE 2U |
SMPCC DFF PROTECT CHECK ENABLE ENABLE.
Definition at line 544 of file core_feature_smpcc.h.
| #define SMPCC_DFF_PROT_CHK_EN_Msk (0x3UL << SMPCC_DFF_PROT_CHK_EN_Pos) |
SMPCC DFF PROTECT CHECK ENABLE Mask.
Definition at line 543 of file core_feature_smpcc.h.
| #define SMPCC_DFF_PROT_CHK_EN_Pos 0U |
SMPCC DFF PROTECT CHECK ENABLE Position.
Definition at line 542 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJCLM_DISABLE 0U |
SMPCC CC_ERR_INJ INJCLM Disable.
Definition at line 296 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJCLM_ENABLE 1U |
SMPCC CC_ERR_INJ INJCLM Enable.
Definition at line 295 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJCLM_Msk (0x1UL << SMPCC_ERR_INJ_INJCLM_Pos) |
SMPCC CC_ERR_INJ INJCLM Mask.
Definition at line 294 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJCLM_Pos 2U |
SMPCC CC_ERR_INJ INJCLM Position.
Definition at line 293 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJDATA_DISABLE 0U |
SMPCC CC_ERR_INJ INJDATA Disable.
Definition at line 286 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJDATA_ENABLE 1U |
SMPCC CC_ERR_INJ INJDATA Enable.
Definition at line 285 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJDATA_Msk (0x1UL << SMPCC_ERR_INJ_INJDATA_Pos) |
SMPCC CC_ERR_INJ INJDATA Mask.
Definition at line 284 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJDATA_Pos 0U |
SMPCC CC_ERR_INJ INJDATA Position.
Definition at line 283 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJECCCODE_Msk (0xFFUL << SMPCC_ERR_INJ_INJECCCODE_Pos) |
SMPCC CC_ERR_INJ INJECCCODE Mask.
Definition at line 304 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJECCCODE_Pos 24U |
SMPCC CC_ERR_INJ INJECCCODE Position.
Definition at line 303 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJMODE_DIRECT 0U |
SMPCC CC_ERR_INJ INJMODE Direct write mode.
Definition at line 300 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJMODE_Msk (0x1UL << SMPCC_ERR_INJ_INJMODE_Pos) |
SMPCC CC_ERR_INJ INJMODE Mask.
Definition at line 299 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJMODE_Pos 3U |
SMPCC CC_ERR_INJ INJMODE Position.
Definition at line 298 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJMODE_XOR 1U |
SMPCC CC_ERR_INJ INJMODE XOR write mode.
Definition at line 301 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJTAG_DISABLE 0U |
SMPCC CC_ERR_INJ INJTAG Disable.
Definition at line 291 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJTAG_ENABLE 1U |
SMPCC CC_ERR_INJ INJTAG Enable.
Definition at line 290 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJTAG_Msk (0x1UL << SMPCC_ERR_INJ_INJTAG_Pos) |
SMPCC CC_ERR_INJ INJTAG Mask.
Definition at line 289 of file core_feature_smpcc.h.
| #define SMPCC_ERR_INJ_INJTAG_Pos 1U |
SMPCC CC_ERR_INJ INJTAG Position.
Definition at line 288 of file core_feature_smpcc.h.
| #define SMPCC_NS_RG_CFG_DISABLE 0x00U |
SMPCC Non-Shareable Region CFG DISABLE.
Definition at line 574 of file core_feature_smpcc.h.
| #define SMPCC_NS_RG_CFG_Msk (0x3UL << SMPCC_NS_RG_CFG_Pos) |
SMPCC Non-Shareable Region CFG Mask.
Definition at line 573 of file core_feature_smpcc.h.
| #define SMPCC_NS_RG_CFG_NACL 0x10U |
SMPCC Non-Shareable Region CFG NACL.
Definition at line 575 of file core_feature_smpcc.h.
| #define SMPCC_NS_RG_CFG_NAPOT 0x11U |
SMPCC Non-Shareable Region CFG NAPOT.
Definition at line 576 of file core_feature_smpcc.h.
| #define SMPCC_NS_RG_CFG_Pos 0U |
SMPCC Non-Shareable Region CFG Position.
Definition at line 572 of file core_feature_smpcc.h.
| #define SMPCC_PMON_CLIENT_SEL_Msk (0x1FUL << SMPCC_PMON_CLIENT_SEL_Pos) |
SMPCC PMON CLIENT SEL Mask.
Definition at line 606 of file core_feature_smpcc.h.
| #define SMPCC_PMON_CLIENT_SEL_Pos 16U |
SMPCC PMON CLIENT SEL Position.
Definition at line 605 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT | ( | event, | |
| client | |||
| ) |
Definition at line 608 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT_DATA_READ_COUNT 1U |
SMPCC PMON EVENT DATA READ COUNT.
Definition at line 594 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT_DATA_READ_HIT_COUNT 4U |
SMPCC PMON EVENT DATA READ HIT COUNT.
Definition at line 597 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT_DATA_READ_MISS_COUNT 7U |
SMPCC PMON EVENT DATA READ MISS COUNT.
Definition at line 600 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT_DATA_READ_REPLACE_COUNT 6U |
SMPCC PMON EVENT DATA READ REPLACE COUNT.
Definition at line 599 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT_DATA_WRITE_COUNT 2U |
SMPCC PMON EVENT DATA WRITE COUNT SABLE.
Definition at line 595 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT_DATA_WRITE_REPLACE_COUNT 5U |
SMPCC PMON EVENT DATA WRITE REPLACE COUNT.
Definition at line 598 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT_DISABLE 0U |
SMPCC PMON EVENT DISABLE.
Definition at line 593 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT_INSTR_READ_COUNT 3U |
SMPCC PMON EVENT INSTR READ COUNT.
Definition at line 596 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT_INSTR_READ_HIT_COUNT 8U |
SMPCC PMON EVENT INSTR READ HIT COUNT.
Definition at line 601 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT_INSTR_READ_MISS_COUNT 9U |
SMPCC PMON EVENT INSTR READ MISS COUNT.
Definition at line 602 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT_INSTR_READ_REPLACE_COUNT 10U |
SMPCC PMON EVENT INSTR READ REPLACE COUNT.
Definition at line 603 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT_SEL_Msk (0xFFFFUL << SMPCC_PMON_EVENT_SEL_Pos) |
SMPCC PMON EVENT SEL Mask.
Definition at line 592 of file core_feature_smpcc.h.
| #define SMPCC_PMON_EVENT_SEL_Pos 0U |
SMPCC PMON EVENT SEL Position.
Definition at line 591 of file core_feature_smpcc.h.
| #define SMPCC_STMCFG_RD_BYTE_THRE_Msk (0x3FFUL << SMPCC_STMCFG_RD_BYTE_THRE_Pos) |
SMPCC READ BYTE THRESHOLD Mask.
Definition at line 507 of file core_feature_smpcc.h.
| #define SMPCC_STMCFG_RD_BYTE_THRE_Pos 0U |
SMPCC READ BYTE THRESHOLD Position.
Definition at line 506 of file core_feature_smpcc.h.
| #define SMPCC_STMCFG_RD_DEGREE_Msk (0x7UL << SMPCC_STMCFG_RD_DEGREE_Pos) |
SMPCC READ DEGREE Mask.
Definition at line 510 of file core_feature_smpcc.h.
| #define SMPCC_STMCFG_RD_DEGREE_Pos 12U |
SMPCC READ DEGREE Position.
Definition at line 509 of file core_feature_smpcc.h.
| #define SMPCC_STMCFG_RD_DISTANCE_Msk (0x7UL << SMPCC_STMCFG_RD_DISTANCE_Pos) |
SMPCC READ DISTANCE Mask.
Definition at line 513 of file core_feature_smpcc.h.
| #define SMPCC_STMCFG_RD_DISTANCE_Pos 16U |
SMPCC READ DISTANCE Position.
Definition at line 512 of file core_feature_smpcc.h.
| #define SMPCC_STMCFG_WR_BYTE_THRE_Msk (0x7FFUL << SMPCC_STMCFG_WR_BYTE_THRE_Pos) |
SMPCC WRITE BYTE THRESHOLD Mask.
Definition at line 516 of file core_feature_smpcc.h.
| #define SMPCC_STMCFG_WR_BYTE_THRE_Pos 20U |
SMPCC WRITE BYTE THRESHOLD Position.
Definition at line 515 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_CROSS_EN_DISABLE 0U |
SMPCC READ STREAM CROSS 4K Disable.
Definition at line 486 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_CROSS_EN_ENABLE 1U |
SMPCC READ STREAM CROSS 4K Enable.
Definition at line 485 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_CROSS_EN_Msk (0x1UL << SMPCC_STMCTRL_CROSS_EN_Pos) |
SMPCC READ STREAM CROSS 4K Enable Mask.
Definition at line 484 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_CROSS_EN_Pos 4U |
SMPCC READ STREAM CROSS 4K Enable Position.
Definition at line 483 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_RD_MERGE_EN_DISABLE 0U |
SMPCC READ Merge Enable Disable.
Definition at line 481 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_RD_MERGE_EN_ENABLE 1U |
SMPCC READ Merge Enable Enable.
Definition at line 480 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_RD_MERGE_EN_Msk (0x1UL << SMPCC_STMCTRL_RD_MERGE_EN_Pos) |
SMPCC READ Merge Enable Mask.
Definition at line 479 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_RD_MERGE_EN_Pos 3U |
SMPCC READ Merge Enable Position.
Definition at line 478 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_RD_STM_EN_DISABLE 0U |
SMPCC READ Stream Enable Disable.
Definition at line 466 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_RD_STM_EN_ENABLE 1U |
SMPCC READ Stream Enable Enable.
Definition at line 465 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_RD_STM_EN_Msk (0x1UL << SMPCC_STMCTRL_RD_STM_EN_Pos) |
SMPCC READ Stream Enable Mask.
Definition at line 464 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_RD_STM_EN_Pos 0U |
SMPCC READ Stream Enable Position.
Definition at line 463 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_TRANS_ALLOC_DISABLE 0U |
SMPCC TRANSLATE ALLOC ATTRIBUTE Disable.
Definition at line 476 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_TRANS_ALLOC_ENABLE 1U |
SMPCC TRANSLATE ALLOC ATTRIBUTE Enable.
Definition at line 475 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_TRANS_ALLOC_Msk (0x1UL << SMPCC_STMCTRL_TRANS_ALLOC_Pos) |
SMPCC TRANSLATE ALLOC ATTRIBUTE Enable Mask.
Definition at line 474 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_TRANS_ALLOC_Pos 2U |
SMPCC TRANSLATE ALLOC ATTRIBUTE Enable Position.
Definition at line 473 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_WR_STM_EN_DISABLE 0U |
SMPCC WRITE Stream Enable Disable.
Definition at line 471 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_WR_STM_EN_ENABLE 1U |
SMPCC WRITE Stream Enable Enable.
Definition at line 470 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_WR_STM_EN_Msk (0x1UL << SMPCC_STMCTRL_WR_STM_EN_Pos) |
SMPCC WRITE Stream Enable Mask.
Definition at line 469 of file core_feature_smpcc.h.
| #define SMPCC_STMCTRL_WR_STM_EN_Pos 1U |
SMPCC WRITE Stream Enable Position.
Definition at line 468 of file core_feature_smpcc.h.
| typedef __IO uint64_t CC_BUS_ERR_ADDR_Type |
Type to access CC_BUS_ERR_ADDR register.
Definition at line 357 of file core_feature_smpcc.h.
| typedef __IO uint64_t CLIENT_ERR_ADDR_Type |
Type to access CLIENT_ERR_ADDR register.
Definition at line 620 of file core_feature_smpcc.h.
| typedef __IO uint64_t SMP_PMON_CNT_Type |
Type to access SMP_PMON_CNT register.
Definition at line 615 of file core_feature_smpcc.h.
1.9.1