NMSIS-Core  Version 1.6.0
NMSIS-Core support for Nuclei processor-based devices
core_feature_iinfo.h
1 /*
2  * Copyright (c) 2019 Nuclei Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Licensed under the Apache License, Version 2.0 (the License); you may
7  * not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  * www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  */
16 #ifndef __CORE_FEATURE_IINFO_H__
17 #define __CORE_FEATURE_IINFO_H__
27 /*
28  * IREGION INFO Configuration Macro:
29  *
30  * 1. __IINFO_BASE: Base address of the IREGION INFO
31  *
32  */
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 #include "core_feature_base.h"
38 
43 #ifdef __IINFO_BASEADDR
44 
56 typedef union {
57  struct {
58  __IM uint32_t cmo_cfg:1;
59  __IM uint32_t cmo_pft:1;
60  __IM uint32_t cmo_size:4;
61  __IM uint32_t cbozero_size:4;
62  uint32_t :22;
63  } b;
64  uint32_t d;
65 } IINFO_MCMO_INFO_Type;
66 
70 typedef union {
71  struct {
72  __IM uint32_t exist:1;
73  __IM uint32_t vector:1;
74  __IM uint32_t vector_b:1;
75  __IM uint32_t vector_k:1;
76  __IM uint32_t smepmp:1;
77  __IM uint32_t sscofpmf:1;
78  __IM uint32_t zfh:1;
79  __IM uint32_t zfhmin:1;
80  __IM uint32_t zfa:1;
81  __IM uint32_t svnapot:1;
82  __IM uint32_t svpbmt:1;
83  __IM uint32_t svinval:1;
84  __IM uint32_t bf16:1;
85  __IM uint32_t zve32x:1;
86  __IM uint32_t zve32f:1;
87  __IM uint32_t zve64x:1;
88  __IM uint32_t zve64f:1;
89  __IM uint32_t zve64d:1;
90  __IM uint32_t zimop:1;
91  __IM uint32_t zcmop:1;
92  __IM uint32_t zicond:1;
93  __IM uint32_t zihintntl:1;
94  __IM uint32_t zihintpause:1;
95  __IM uint32_t zvfh:1;
96  __IM uint32_t zvfhmin:1;
97  __IM uint32_t smrnmi:1;
98  __IM uint32_t zihpm:1;
99  __IM uint32_t smcntrpmf:1;
100  __IM uint32_t zicntr:1;
101  __IM uint32_t zawrs:1;
102  uint32_t :2;
103  } b;
104  uint32_t d;
105 } IINFO_ISA_SUPPORT0_Type;
106 
110 typedef union {
111  struct {
112  __IM uint32_t exist:1;
113  __IM uint32_t ssqosid:1;
114  __IM uint32_t zicflip:1;
115  __IM uint32_t zicfiss:1;
116  __IM uint32_t smctr:1;
117  __IM uint32_t zacas:1;
118  __IM uint32_t zabha:1;
119  __IM uint32_t smdbltrp:1;
120  __IM uint32_t ssdbltrp:1;
121  __IM uint32_t smcdeleg:1;
122  __IM uint32_t smmpm:1;
123  __IM uint32_t smnpm:1;
124  __IM uint32_t ssnpm:1;
125  __IM uint32_t smstateen:1;
126  __IM uint32_t sstateen:1;
127  __IM uint32_t smcsrind:1;
128  __IM uint32_t sscsrind:1;
129  __IM uint32_t svadu:1;
130  uint32_t :14;
131  } b;
132  uint32_t d;
133 } IINFO_ISA_SUPPORT1_Type;
134 
138 typedef union {
139  struct {
140  __IM uint32_t exist:1;
141  __IM uint32_t fpu_cycle:5;
142  __IM uint32_t high_div:1;
143  __IM uint32_t dcache_2stage:1;
144  __IM uint32_t delay_branch_flush:1;
145  __IM uint32_t bus_type:3;
146  __IM uint32_t dual_issue:1;
147  __IM uint32_t cross_4k:1;
148  __IM uint32_t dlm_2stage:1;
149  __IM uint32_t lsu_cut_fwd:1;
150  __IM uint32_t dsp_cycle:4;
151  __IM uint32_t ifu_cut_timing:1;
152  __IM uint32_t mem_cut_timing:1;
153  __IM uint32_t dcache_prefetch:1;
154  __IM uint32_t dcache_lbuf_num:5;
155  __IM uint32_t mul_cyc:3;
156  uint32_t :1;
157  } b;
158  uint32_t d;
159 } IINFO_PERFORMANCE_CFG0_Type;
160 
164 typedef union {
165  struct {
166  __IM uint32_t exist:1;
167  __IM uint32_t vfpu_cyc:5;
168  __IM uint32_t bht_entry_width:5;
169  __IM uint32_t high_performance:1;
170  __IM uint32_t agu_quick_forward:1;
171  __IM uint32_t cau_fwd:1;
172  __IM uint32_t hpm_ver:2;
173  uint32_t :16;
174  } b;
175  uint32_t d;
176 } IINFO_PERFORMANCE_CFG1_Type;
177 
181 typedef union {
182  struct {
183  __IOM uint32_t l1d_ena:1;
184  __IOM uint32_t cc_ena:1;
185  __IOM uint32_t scalar_ena:1;
186  __IOM uint32_t vector_ena:1;
187  __IOM uint32_t write_pref_ena:1;
188  __IOM uint32_t cross_page_pref_ena:1;
189  __IOM uint32_t mmu_ena:1;
190  __IOM uint32_t pl2_ena:1;
191  __IOM uint32_t pref_conflict_stop_th:4;
192  __IOM uint32_t pref_conflict_decr_sel:3;
193  uint32_t :17;
194  } b;
195  struct {
211  __IM uint32_t level:8;
212  __IM uint32_t pref_conflict_stop_th:4;
213  __IM uint32_t pref_conflict_decr_sel:3;
214  uint32_t :17;
215  } lv;
216  uint32_t d;
217 } IINFO_PFL1DCTRL1_Type;
218 
219 #define IINFO_PFL1DCTRL1_LEVEL_Pos (1UL << 0) /* IINFO PFL1DCTRL1 level position */
220 #define IINFO_PFL1DCTRL1_LEVEL_Msk (0xFFUL << IINFO_PFL1DCTRL1_LEVEL_Pos) /* IINFO PFL1DCTRL1 level mask */
221 
222 #define IINFO_PFL1DCTRL1_DISABLE (0UL)
223 #define IINFO_PFL1DCTRL1_L1D_ENA (1UL << 0)
224 #define IINFO_PFL1DCTRL1_CC_ENA (1UL << 1)
225 #define IINFO_PFL1DCTRL1_SCALAR_ENA (1UL << 2)
226 #define IINFO_PFL1DCTRL1_VECTOR_ENA (1UL << 3)
227 #define IINFO_PFL1DCTRL1_WRITE_PREF_ENA (1UL << 4)
228 #define IINFO_PFL1DCTRL1_CROSS_PAGE_PREF_ENA (1UL << 5)
229 #define IINFO_PFL1DCTRL1_MMU_PREF_ENA (1UL << 6)
230 #define IINFO_PFL1DCTRL1_PL2_ENA (1UL << 7)
235 typedef union {
236  struct {
237  __IOM uint32_t degree_incr_th:6;
238  __IOM uint32_t degree_decr_th:6;
239  __IOM uint32_t next_line_ena_th:4;
240  __IOM uint32_t write_noalloc_l1_th:2;
241  __IOM uint32_t write_noalloc_l2_th:2;
242  uint32_t :12;
243  } b;
244  uint32_t d;
245 } IINFO_PFL1DCTRL2_Type;
246 
250 typedef union {
251  struct {
252  __IOM uint32_t ws_tmout_max:12;
253  uint32_t :4;
254  __IOM uint32_t nc_tmout_max:8;
255  __IOM uint32_t dev_store_early_ret: 1;
256  uint32_t :7;
257  } b;
258  uint32_t d;
259 } IINFO_MERGEL1DCTRL_Type;
260 
264 typedef union {
265  struct {
266  __IOM uint32_t reg_prot_chck_en:2;
267  uint32_t :30;
268  } b;
269  uint32_t d;
270 } IINFO_SAFETY_CTRL_Type;
271 
275 typedef union {
276  struct {
277  uint32_t :1;
278  __IOM uint32_t pf_access: 1;
279  __IOM uint32_t cache_csr_access: 1;
280  __IOM uint32_t pma_csr_access: 1;
281  uint32_t :28;
282  } b;
283  uint32_t d;
284 } IINFO_ACCESS_CTRL_Type;
285 
289 typedef union {
290  struct {
291  __IOM uint32_t max_stream_l1_degree:4;
292  uint32_t :1;
293  __IOM uint32_t max_stream_l2_degree:7;
294  uint32_t :4;
295  __IOM uint32_t max_stride_cplx_l1_degree:4;
296  uint32_t :1;
297  __IOM uint32_t max_stride_cplx_l2_degree:7;
298  uint32_t :4;
299  } b;
300  uint32_t d;
301 } IINFO_PFL1DCTRL3_Type;
302 
306 typedef union {
307  struct {
308  __IOM uint32_t pf_enable:1;
309  __IOM uint32_t cc_short_enable:1;
310  uint32_t :30;
311  } b;
312  uint32_t d;
313 } IINFO_PFL1DCTRL4_Type;
314 
318 typedef union {
319  struct {
320  __IM uint32_t pf_cfg:8;
321  __IM uint32_t l2_pf_lbuf_num:8;
322  __IM uint32_t l2_pf_dbuf_num:8;
323  __IM uint32_t pf_ver:8;
324  } b;
325  uint32_t d;
326 } IINFO_PFL1INFO_Type;
327 
331 typedef union {
332  struct {
333  uint32_t inject_way:8;
334  uint32_t :22;
335  uint32_t security_mode:1;
336  uint32_t precise_ecc_inject:1;
337  } b;
338  uint32_t d;
339 } IINFO_ECC_INJ_WAY_Type;
340 
341 /* IREGION INFO Memory-Mapped Register Type*/
342 typedef struct {
343  __IM uint32_t mpasize;
344  __IM IINFO_MCMO_INFO_Type cmo_info;
345  __IM uint32_t sec_base_addr_lo;
346  __IM uint32_t sec_base_addr_hi;
347  __IM uint32_t sec_cfg_info;
348  __IM uint32_t reserved0[4];
349  __IM uint32_t mvlm_cfg_lo;
350  __IM uint32_t mvlm_cfg_hi;
351  __IM uint32_t flash_base_addr_lo;
352  __IM uint32_t flash_base_addr_hi;
353  __IM uint32_t reserved1[7];
354  __IM uint32_t vpu_cfg_info;
355  __IOM uint32_t mem_region0_cfg_lo;
356  __IM uint32_t mem_region0_cfg_hi;
357  __IOM uint32_t mem_region1_cfg_lo;
358  __IM uint32_t mem_region1_cfg_hi;
359  uint32_t reserved2[3];
360  __IM IINFO_ISA_SUPPORT0_Type isa_support0;
361  __IM IINFO_ISA_SUPPORT1_Type isa_support1;
362  uint32_t reserved3[2];
363  __IOM uint32_t mcppi_cfg_lo;
364  __IM uint32_t mcppi_cfg_hi;
365  __IOM uint32_t mpftctl;
366  uint32_t reserved4;
367  __IM IINFO_PERFORMANCE_CFG0_Type performance_cfg0;
368  __IM IINFO_PERFORMANCE_CFG1_Type performance_cfg1;
369  uint32_t reserved5[26];
370  __IOM IINFO_PFL1DCTRL1_Type pfl1dctrl1;
371  __IOM IINFO_PFL1DCTRL2_Type pfl1dctrl2;
372  __IOM IINFO_MERGEL1DCTRL_Type mergel1dctrl;
373  uint32_t reserved6;
374  __IOM IINFO_SAFETY_CTRL_Type safety_ctrl;
375  __IOM IINFO_ACCESS_CTRL_Type access_ctrl;
376  uint32_t reserved7[2];
377  __IOM IINFO_PFL1DCTRL3_Type pfl1dctrl3;
378  __IOM IINFO_PFL1DCTRL4_Type pfl1dctrl4;
379  __IM IINFO_PFL1INFO_Type pfl1info;
380  uint32_t reserved8[27];
381  __IOM uint32_t crc_rf0;
382  __IOM uint32_t crc_rf1;
383  __IOM uint32_t crc_fp0;
384  __IM uint32_t etrace_info;
385  __IOM uint32_t ecc_inj_addr_lo;
386  __IOM uint32_t ecc_inj_addr_hi;
387  __IOM IINFO_ECC_INJ_WAY_Type ecc_inj_way;
388  uint32_t reserved9[83];
389  __IOM uint32_t mem_crc_x22_lo;
390  __IOM uint32_t mem_crc_x22_hi;
391  __IOM uint32_t mem_crc_x23_lo;
392  __IOM uint32_t mem_crc_x23_hi;
393  __IOM uint32_t mem_crc_f23_lo;
394  __IOM uint32_t mem_crc_f23_hi;
395 } IINFO_Type;
396 
397 /* IREGION INFO Memory mapping of Device */
398 #define IINFO_BASE __IINFO_BASEADDR
399 #define IINFO ((IINFO_Type *)IINFO_BASE)
404 typedef enum {
405  IINFO_HPM_VER_UNKNOWN = 0,
406  IINFO_HPM_VER_1,
407  IINFO_HPM_VER_2,
408  IINFO_HPM_VER_MAX
409 } IINFO_HPM_VER_Type;
410  /* end of group NMSIS_Core_IINFO_Registers */
412 
427 __STATIC_FORCEINLINE int32_t IINFO_IsCMOSupported(void)
428 {
429  return IINFO->cmo_info.b.cmo_cfg;
430 }
431 
438 __STATIC_FORCEINLINE int32_t IINFO_IsCMOPrefetchSupported(void)
439 {
440  return IINFO->cmo_info.b.cmo_cfg && IINFO->cmo_info.b.cmo_pft;
441 }
442 
450 __STATIC_FORCEINLINE IINFO_HPM_VER_Type IINFO_GetHPMVersion(void)
451 {
452  if (!IINFO->performance_cfg1.b.exist) {
453  return IINFO_HPM_VER_UNKNOWN;
454  }
455  return (IINFO_HPM_VER_Type)IINFO->performance_cfg1.b.hpm_ver;
456 }
457 
493 __STATIC_FORCEINLINE void IINFO_SetPrefetchLevel(uint32_t val)
494 {
495  IINFO->pfl1dctrl1.d = (IINFO->pfl1dctrl1.d & ~IINFO_PFL1DCTRL1_LEVEL_Msk) |
496  _VAL2FLD(IINFO_PFL1DCTRL1_LEVEL, val);
497 }
498 
506 __STATIC_FORCEINLINE uint32_t IINFO_GetPrefetchLevel(void)
507 {
508  return IINFO->pfl1dctrl1.lv.level;
509 }
510 
516 __STATIC_FORCEINLINE void IINFO_SetPFL1DCTRL2(uint32_t val)
517 {
518  IINFO->pfl1dctrl2.d = val;
519 }
520 
526 __STATIC_FORCEINLINE uint32_t IINFO_GetPFL1DCTRL2(void)
527 {
528  return IINFO->pfl1dctrl2.d;
529 }
530 
536 __STATIC_FORCEINLINE void IINFO_SetPFL1DCTRL3(uint32_t val)
537 {
538  IINFO->pfl1dctrl3.d = val;
539 }
540 
546 __STATIC_FORCEINLINE uint32_t IINFO_GetPFL1DCTRL3(void)
547 {
548  return IINFO->pfl1dctrl3.d;
549 }
550 
555 __STATIC_FORCEINLINE void IINFO_EnablePrefetchOverall(void)
556 {
557  IINFO->pfl1dctrl4.b.pf_enable = 1;
558 }
559 
564 __STATIC_FORCEINLINE void IINFO_DisablePrefetchOverall(void)
565 {
566  IINFO->pfl1dctrl4.b.pf_enable = 0;
567 }
568 
575 __STATIC_FORCEINLINE int32_t IINFO_IsPreciseECCInjSupported(void)
576 {
577  return IINFO->ecc_inj_way.b.precise_ecc_inject;
578 }
579 
587 __STATIC_FORCEINLINE void IINFO_SetPreciseECCInjWay(void *addr, uint8_t way)
588 {
589  unsigned long rv_addr = (unsigned long)addr;
590  IINFO->ecc_inj_addr_lo = (uint32_t)rv_addr;
591  IINFO->ecc_inj_addr_hi = (uint32_t)((uint64_t)rv_addr >> 32);
592  IINFO->ecc_inj_way.b.inject_way = way;
593 }
594  /* End of Doxygen Group NMSIS_Core_IINFO_Functions */
596 
597 #endif /* #ifdef __IINFO_BASEADDR */
598 
599 #ifdef __cplusplus
600 }
601 #endif
602 #endif /* __CORE_FEATURE_IINFO_H__ */
603 
__STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE
Define a static function that should be always inlined by the compiler.
Definition: nmsis_gcc.h:70
_VAL2FLD
#define _VAL2FLD(field, value)
Mask and shift a bit field value for use in a register bit range.
Definition: nmsis_compiler.h:84
__IM
#define __IM
Defines 'read only' structure member permissions.
Definition: nmsis_compiler.h:65
__IOM
#define __IOM
Defines 'read/write' structure member permissions.
Definition: nmsis_compiler.h:69